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PDF ADC08D1010 Data sheet ( Hoja de datos )
| Número de pieza | ADC08D1010 | |
| Descripción | 1 GSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
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ADC08D1010
April 20, 2009
www.DataSheet4U.com
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
The ADC08D1010 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.0 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing 6.9 ENOB with a 500 MHz input signal and a 1 GHz
sample rate while providing a 10-15 B.E.R. Output formatting
is offset binary and the LVDS digital outputs are compliant
with IEEE 1596.3-1996, with the exception of an adjustable
common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C ≤ TA ≤ +85°C) temperature range.
Features
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ Interleave Mode for 2x Sampling Rate
■ Multiple ADC Synchronization Capability
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Fine Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
Key Specifications
■ Resolution
■ Max Conversion Rate
■ Bit Error Rate
■ ENOB @ 500 MHz Input
■ DNL
■ Power Consumption
■ — Operating
— Power Down Mode
8 Bits
1 GSPS (min)
10-15 (typ)
6.9 Bits (typ)
±0.15 LSB (typ)
1.6 W (typ)
3.5 mW (typ)
Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation
Block Diagram
© 2009 National Semiconductor Corporation 201467
20146753
www.national.com
1 page  
Pin Functions
Pin No.
Symbol
32 REXT
Equivalent Circuit
Description
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External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
34 Tdiode_P
35 Tdiode_N
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
79 OR+
80 OR-
82 DCLK+
81 DCLK-
Temperature Diode Positive (Anode) and Negative (Cathode).
These pins may be used for die temperature measurements,
however no specified accuracy is implied or guaranteed. Noise
coupling from adjacent output data signals has been shown to
affect temperature measurements using this feature. See Section
2.6.2.
I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
these outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω differential
resistor.
Out Of Range output. A differential high at these pins indicates that
the differential input is out of range (outside the range as defined
by the FSR pin).
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode.
5 www.national.com
5 Page 
Symbol
tHLT
tOSK
tSU
tH
tAD
tAJ
tOD
tWU
fSCLK
tSSU
tSH
tCAL
tCAL_L
Parameter
Conditions
Differential High to Low Transition
Time
10% to 90%, CL = 2.5 pF
DCLK to Data Output Skew
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)
Data to DCLK Set-Up Time
DDR Mode, 90° DCLK (Note 11)
DCLK to Data Hold Time
DDR Mode, 90° DCLK (Note 11)
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
Aperture Jitter
Input Clock to Data Output Delay 50% of Input Clock transition to 50% of
(in addition to Pipeline Delay) Data transition
DI Outputs
DId Outputs
Pipeline Delay (Latency)
(Notes 11, 14)
DQ Outputs
Normal Mode
DES Mode
DQd Outputs
Normal Mode
DES Mode
Over Range Recovery Time
Differential VIN step from ±1.2V to 0V to
get accurate conversion
PD low to Rated Accuracy
Conversion (Wake-Up Time)
DCS
(Note 11)
Serial Clock Frequency
(Note 11)
Data to Serial Clock Setup Time (Note 11)
Data to Serial Clock Hold Time (Note 11)
Serial Clock Low Time
Serial Clock High Time
Calibration Cycle Time
CAL Pin Low Time
See Figure 9(Note 11)
Typical
(Note 8)
250
±50
750
890
1.3
0.4
3.1
1
500
1
100
2.5
1
1.4 x 105
tCAL_H
tCalDly
CAL Pin High Time
See Figure 9(Note 11)
Calibration delay determined by
pin 127 state.
CalDly = Low
See 1.1.1 Self Calibration, Figure 9,
(Note 11)
CalDly = High
See 1.1.1, Self Calibration, Figure 9,
(Note 11)
Limits
(Note 8)
13
14
13
13.5
14
14.5
4
4
80
80
225
231
Units
(Limits)
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ps
ps (max)
ps
ps
ns
ps rms
ns
Input Clock
Cycles
Input Clock
Cycle
ns
µs
MHz
ns (min)
ns (min)
ns (min)
ns (min)
Clock Cycles
Clock Cycles
(min)
Clock Cycles
(min)
Clock Cycles
(min)
Clock Cycles
(max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
11 www.national.com
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| Páginas | Total 38 Páginas | |
| PDF Descargar | [ Datasheet ADC08D1010.PDF ] | |
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