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PDF 74LVC2T45 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2T45 | |
| Descripción | Dual supply translating transceiver | |
| Fabricantes | NXP Semiconductors | |
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74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
Rev. 03 — 19 January 2010
Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A)
and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and
pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114E Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
1 page  
NXP Semiconductors
8. Limiting values
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC(A)
VCC(B)
IIK
VI
IOK
VO
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
VI < 0 V
VO < 0 V
Active mode
Suspend or 3-state mode
−0.5
−0.5
−50
[1] −0.5
−50
[1][2][3] −0.5
[1] −0.5
+6.5
+6.5
-
+6.5
-
VCCO + 0.5
+6.5
V
V
mA
V
mA
V
V
IO output current
VO = 0 V to VCCO
[2] -
±50 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
ICC(A) or ICC(B)
Tamb = −40 °C to +125 °C
-
−100
−65
[4] -
100
-
+150
250
mA
mA
°C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
VO
Tamb
Δt/ΔV
Recommended operating conditions
Parameter
Conditions
supply voltage A
supply voltage B
input voltage
output voltage
Active mode
Suspend or 3-state mode
ambient temperature
input transition rise and fall rate
VCCI = 1.2 V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
Min
1.2
1.2
0
[1] 0
0
−40
[2] -
-
-
-
-
Max
5.5
5.5
5.5
VCCO
5.5
+125
20
20
20
10
5
Unit
V
V
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
ns/V
74LVC_LVCH2T45_3
Product data sheet
Rev. 03 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
www.DataSheet4U.com
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
1.8 V
VCC(A) and VCC(B)
2.5 V
3.3 V
CPD power dissipation A port: (direction A to B);
2
3
3
capacitance
B port: (direction B to A)
A port: (direction B to A); 15 16 16
B port: (direction A to B)
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
5.0 V
4
Unit
pF
18 pF
Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH LOW to HIGH
propagation delay
A to B
B to A
2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns
2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
tPHL HIGH to LOW
A to B
propagation delay B to A
2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns
2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns
tPHZ HIGH to OFF-state DIR to A
propagation delay DIR to B
3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns
3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
tPLZ LOW to OFF-state DIR to A
propagation delay DIR to B
2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns
2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 ns
tPZH OFF-state to HIGH DIR to A [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns
propagation delay DIR to B [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns
tPZL OFF-state to LOW DIR to A [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns
propagation delay DIR to B [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns
VCC(A) = 1.65 V to 1.95 V
tPLH LOW to HIGH
propagation delay
A to B
B to A
2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 ns
2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns
tPHL HIGH to LOW
A to B
propagation delay B to A
2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 ns
2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns
tPHZ HIGH to OFF-state DIR to A
propagation delay DIR to B
2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns
3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5 8.2 ns
tPLZ LOW to OFF-state DIR to A
propagation delay DIR to B
2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns
2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 7.1 ns
74LVC_LVCH2T45_3
Product data sheet
Rev. 03 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 74LVC2T45.PDF ] | |
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