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PDF 74LVC2G241 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G241 | |
| Descripción | Dual buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC2G241
Dual buffer/line driver; 3-state
Rev. 07 — 5 October 2007
www.DataSheet4U.com
Product data sheet
1. General description
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE:
• A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
• A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8-B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I Inputs accept voltages up to 5 V
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page  
NXP Semiconductors
74LVC2G241
www.DataSheet4U.com
Dual buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Tamb
∆t/∆V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
ambient temperature
VCC = 1.65 V to 5.5 V; enable mode
VCC = 1.65 V to 5.5 V; disable mode
VCC = 0 V; Power-down mode
input transition rise
and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
10. Static characteristics
Min Typ Max Unit
1.65 -
5.5 V
0-
5.5 V
0-
0-
VCC
V
5.5 V
0-
5.5 V
−40 -
+125 °C
- - 20 ns/V
- - 10 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Min
Tamb = −40 °C to +85 °C[1]
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65VCC
1.7
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
2.0
0.7VCC
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
-
VCC = 2.3 V to 2.7 V
-
VCC = 2.7 V to 3.6 V
-
VCC = 4.5 V to 5.5 V
-
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
-
-
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
-
-
IO = 24 mA; VCC = 3.0 V
-
IO = 32 mA; VCC = 4.5 V
-
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VCC − 0.1
1.2
1.9
2.2
2.3
3.8
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
Typ Max
Unit
--
V
--
V
--
V
--
V
- 0.35VCC V
- 0.7
V
- 0.8
V
- 0.3VCC V
- 0.1
V
- 0.45 V
- 0.3
V
- 0.4
V
- 0.55 V
- 0.55 V
--
--
--
--
--
--
±0.1 ±5
V
V
V
V
V
V
µA
74LVC2G241_7
Product data sheet
Rev. 07 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
74LVC2G241
www.DataSheet4U.com
Dual buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
y
Z
8
5
c
E AX
HE v M A
pin 1 index
1
e
4
bp w M
A A2
A1
(A3)
detail X
Lp
L
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
D(1)
3.1
2.9
E(1) e
3.1
2.9
0.65
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
HE
4.1
3.9
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT505-2
---
L Lp v w y Z(1)
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
θ
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
Fig 10. Package outline SOT505-2 (TSSOP8)
74LVC2G241_7
Product data sheet
Rev. 07 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
11 of 17
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| PDF Descargar | [ Datasheet 74LVC2G241.PDF ] | |
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