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PDF NTD4808N Data sheet ( Hoja de datos )

Número de pieza NTD4808N
Descripción Power MOSFET ( Transistor )
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NTD4808N
Power MOSFET
30 V, 63 A, Single N−Channel, DPAK/IPAK
Features
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
Applications
CPU Power Delivery
DC−DC Converters
www.DataLShoewetS4iUd.ce oSmwitching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJA
(Note 1)
VDSS 30 V
VGS 20 V
TA = 25°C
ID
12 A
TA = 85°C
9.5
Power Dissipation
RqJA (Note 1)
Continuous Drain
Current RqJA
(Note 2)
Power Dissipation
RqJA (Note 2)
Continuous Drain
Current RqJC
(Note 1)
TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
PD
ID
PD
ID
2.0 W
9.8 A
7.5
1.3 W
63 A
49
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
TC = 25°C
tp=10ms TA = 25°C
PD
IDM
54.6 W
126 A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 30 V, VGS = 10 V,
IL = 17 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
IDmaxPkg
TJ,
TSTG
IS
dV/dt
EAS
TL
45
−55 to
+175
45
6
144.5
260
A
°C
A
V/ns
mJ
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
8.0 mW @ 10 V
12.4 mW @ 4.5 V
D
ID MAX
63 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
DPAK
CASE 369C
STYLE 2
1 23
1
2
3
3 IPAK
DPAK
(STRAIGHT LEAD) CASE 369D
CASE 369AC
STYLE 2
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4808N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 0
1
Publication Order Number:
NTD4808N/D

1 page




NTD4808N pdf
NTD4808N
TYPICAL PERFORMANCE CURVES
2000
1500
TJ = 25°C
Ciss
1000
500 Coss
0 Crss
0 5 10 15 20 25
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GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
5
4 Q1
QT
Q2
3
2
VDD = 15 V
1 VGS = 4.5 V
ID = 30 A
0 TJ = 25°C
0 1 2 3 4 5 6 7 8 9 10 11 12
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
100
tr
td(off)
10
td(on)
tf
1
1
VDD = 15 V
ID = 30 A
VGS = 11.5 V
10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
30
VGS = 0 V
25 TJ = 25°C
20
15
10
5
0
0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 ms
100 ms
10 1 ms
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 ms
dc
1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
100
90 ID = 17 A
80
70
60
50
40
30
20
10
0
50
75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
175
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
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