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PDF M65KA128AE Data sheet ( Hoja de datos )
| Número de pieza | M65KA128AE | |
| Descripción | Low Power SDRAM | |
| Fabricantes | STMicroelectronics | |
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M65KA128AE
128Mbit (4 Banks x 2M x 16)
1.8 V Supply, Low Power SDRAM
Features summary
■ 128Mbit Synchronous Dynamic RAM
– Organized as 4 Banks of 2MWords, each
16 bits wide
■ Synchronous Burst Read and Write
www.DataShe–et4FUi.xceodmBurst Lengths: 1, 2, 4, 8 Words or
Full Page
– Burst Types: Sequential and Interleaved.
– Maximum Clock frequency: 133MHz
– Clock Valid to Output Delay (CAS Latency):
3 at maximum clock frequency
– Burst Control by Burst Stop and Precharge
Command
■ Supply Voltage
– VDD = VDDQ = 1.7 to 1.95V
■ Automatic and controlled Precharge
■ Byte control by LDQM and UDQM
■ Low-power features:
– Partial Array Self Refresh (PASR),
– Automatic Temperature Compensated Self
Refresh (TCSR)
– Driver Strength (DS)
– Deep Power-Down Mode
■ Auto Refresh and Self Refresh
■ LVCMOS Interface compatible with
multiplexed addressing
■ Operating temperature range
– − 25 to 90°C
Wafer
M65KA128AE IS ONLY AVAILABLE AS PART OF A MULTIPLE MEMORY PRODUCT
August 2006
Rev 1
1/53
www.st.com
1
1 page  
M65KA128AE
List of tables
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Self-Refresh Current (IDD6) Values in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . 26
Table 12. AC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
www.DataTSahbeleet41U3.c.om AC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5/53
5 Page 
M65KA128AE
3 Operations
Operations
There are 7 operating modes that control the memory. Each of these is described in this
section, see Table 2: Operating Modes, for a summary.
3.1 Power-Up
The Low-Power SDRAM has to be powered up and initialized in a well determined manner.
Power must be applied to VDD and VDDQ simultaneously and, at the same time, the clock
signal must be started. After Power-Up, a minimum initial pause of 200µs is required. From
power-up until the Precharge command is issued, the KE and DQM signals must be held
High.
www.DataSheet4U.com
The Precharge
cycles must be
command must then be issued
executed after the precharge is
to all banks, and 2
completed and the
or more Auto
minimum tRP
Refresh
is satisfied.
Once these cycles are completed, a Mode Register Set command must be issued to
program the specific operation mode (CAS Latency, Burst Length, etc.). After issuing the
Mode Register Set command, the device will not accept any other command for tRSC. An
Extended Mode Register Set command must also be issued to program the Self Refresh
operation mode (PASR and DS). After issuing the Extended Mode Register Set command
the device will not accept any other command for tRSC.
The Auto refresh, mode register programming and extended mode register programming
can be performed in a random sequence.
CKE and DQM must be held high until the Precharge command is issued to ensure the data
bus High-Z level.
The device is now ready for normal operation.
Refer to Figure 22 for a detailed description of the Power-Up AC waveforms.
3.2 Burst Read
The Read command is used to switch the device to Burst Read mode (see Section 4.5:
Read command for details). In Burst Read mode the data is output in bursts synchronized
with the clock. A valid Burst Read operation is initiated by driving E and CAS Low, VIL, and
W and RAS High, VIH, at the positive edge of the clock signal, K.
Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the
Burst Read operation will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’),
the row will remain active for subsequent accesses.
BA1 and BA0 are used to select the bank, and the A8-A0 address inputs are used to select
the starting column location. During a Burst Read operation, the memory reads data from
the activated bank. The Burst Length (1, 2, 4, 8 Words or full page), Burst Type (sequential
or interleaved), and CAS Latency depend on the values programmed by issuing a Mode
Register Set command (see Section 5.1: Mode Register description).
After a Burst Read operation is completed, data outputs become High-Z.
Refer to Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for a
detailed description of Burst Read AC waveforms.
11/53
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