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PDF PCA9549 Data sheet ( Hoja de datos )
| Número de pieza | PCA9549 | |
| Descripción | Octal bus switch | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9549
Octal bus switch with individually I2C-bus controlled enables
Rev. 01 — 11 July 2006
Product data sheet
1. General description
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The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled
by the I2C-bus. The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. Any individual A to B channel or combination of channels
can be selected via the I2C-bus, determined by the contents of the programmable Control
register. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow from
Port A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,
creating a high-impedance state between the two ports, which stops the data flow.
An active LOW reset input (RESET) allows the PCA9549 to recover from a situation
where the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus
state machine and causes all the bits to be open, as does the internal power-on reset
function.
Three address pins allow up to eight devices on the same bus.
2. Features
I 8-bit bus switch (CBT)
I 5 Ω switch connection between two ports
I I2C-bus interface logic; compatible with SMBus standards
I Active LOW RESET input
I 3 address pins allowing up to 8 devices on the I2C-bus
I Bit selection via I2C-bus, in any combination
I Power-up with all bits deselected
I Low Ron switches
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO24, TSSOP24, HVQFN24
1 page  
Philips Semiconductors
PCA9549
Octal bus switch with individually I2C-bus controlled enables
6. Functional description
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9549 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
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1 1 1 0 A2 A1 A0 R/W
fixed
hardware
selectable
002aaa962
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9549, which will be stored in the Control register. If multiple bytes are
received by the PCA9549, it will save the last byte received. This register can be written
and read via the I2C-bus.
Fig 6. Control register
channel selection bits
(read/write)
76543210
B7 B6 B5 B4 B3 B2 B1 B0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
002aab254
6.2.1 Control register definition
One or several bits are selected by the contents of the Control register. This register is
written after the PCA9549 has been addressed. The entire control byte is used to
determine which bit is to be selected. When a bit is selected to close, the bit will close
after the Acknowledge has been placed on the I2C-bus.
PCA9549_1
Product data sheet
Rev. 01 — 11 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 24
5 Page 
Philips Semiconductors
PCA9549
Octal bus switch with individually I2C-bus controlled enables
9. Static characteristics
Table 6. Static characteristics
VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
See Table 7 on page 12 for VDD = 4.5 V to 5.5 V[1].
Symbol Parameter
Conditions
Min
Supply
VDD supply voltage
IDD supply current
Operating mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 100 kHz
Istb standby current
Standby mode; VDD = 3.6 V; no load;
w w w . D a t a S h e e t 4 U . c o m VI = VDD or VSS
VPOR
power-on reset voltage no load; VI = VDD or VSS
Input SCL; input/output SDA
2.3
-
-
[2] -
VIL LOW-level input voltage
VIH HIGH-level input voltage
IOL LOW-level output current
IL leakage current
Ci input capacitance
Select inputs A0 to A2, RESET
VOL = 0.4 V
VOL = 0.6 V
VI = VDD or VSS
VI = VSS
−0.5
0.7VDD
3
6
−1
-
VIL LOW-level input voltage
VIH HIGH-level input voltage
ILI input leakage current
Ci input capacitance
Pass gate
pin at VDD or VSS
VI = VSS
−0.5
0.7VDD
−1
-
Ron
Vo(sw)
IL
Cio
ON-state resistance
switch output voltage
leakage current
input/output capacitance
VDD = 3.0 V to 3.6 V; VO = 0.4 V;
IO = 15 mA
VDD = 2.3 V to 2.7 V; VO = 0.4 V;
IO = 10 mA
Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA
Vi(sw) = VDD = 3.0 V to 3.6 V;
Io(sw) = −100 µA
Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA
Vi(sw) = VDD = 2.3 V to 2.7 V;
Io(sw) = −100 µA
VI = VDD or VSS
VI = VSS
-
-
-
1.6
-
1.0
−1
-
[1] For operation between published voltage ranges, refer to the worst-case parameters in both ranges.
[2] VDD must be lowered to 0.2 V in order to reset part.
Typ
-
20
0.1
1.6
-
-
-
-
-
6
-
-
-
2
7
8
1.9
-
1.5
-
-
3
Max Unit
3.6 V
50 µA
1 µA
2.1 V
+0.3VDD
6
-
-
+1
21
V
V
mA
mA
µA
pF
+0.3VDD
VDD + 0.5
+1
5
V
V
µA
pF
12 Ω
15 Ω
-V
2.8 V
-V
2.0 V
+1 µA
5 pF
PCA9549_1
Product data sheet
Rev. 01 — 11 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PCA9549.PDF ] | |
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