PDF AD9973 Data sheet ( Hoja de datos )

Número de pieza	AD9973
Descripción	14-Bit CCD Signal Processor
Fabricantes	Analog Devices
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No Preview Available ! Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing™ Core AD9973 FEATURES 1.8 V analog and digital core supply voltage Serial data link with reduced range LVDS outputs Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) 14-bit, 65 MHz analog-to-digital converter Black level clamp with variable level control Complete on-chip timing generator www.DParteacSishieonetT4iUm.cinogmcore with 240 ps resolution @ 65 MHz On-chip 3 V horizontal and RG drivers 6 mm × 6 mm, 84-ball CSP_BGA package APPLICATIONS Professional HDTV camcorders Professional, high-end digital cameras Broadcast cameras Industrial high speed cameras GENERAL DESCRIPTION The AD9973 is a highly integrated dual channel CCD signal processor for high speed digital video camera applications. Each channel is specified at pixel rates of up to 65 MHz, and consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with 240 ps resolution at 65 MHz operation. The AD9973 also contains a reduced range LVDS interface for the dual-channel data outputs. Each analog front end (AFE) includes black level clamping, CDS, VGA, and a 65 MSPS, 14-bit analog-to-digital converter. The timing driver provides the high speed CCD clock drivers for RG, HL, and H1 to H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving 6 mm × 6 mm, 84-ball CSP_BGA, the AD9973 is specified over an operating temperature range of −25°C to +85°C. CCDINP_A CCDINM_A CCDINP_B CCDINM_B LDO_OUT_A LDO_OUT_B RG_A RG_B HLA, H1A TO H4A HLB, H1B TO H4B FUNCTIONAL BLOCK DIAGRAM REFT_A REFB_A REFT_B REFB_B AD9973 VREF_A VREF_B CDS –3dB, 0dB, +3dB, +6dB VGA 6dB ~ 42dB CDS –3dB, 0dB, +3dB, +6dB 6dB ~ 42dB VGA ADC CLAMP CLAMP ADC REDUCED RANGE LVDS INTERFACE 1.8V OUTPUT LDO A 1.8V OUTPUT LDO B INTERNAL CLOCKS 5 HORIZONTAL DRIVERS 5 PRECISION TIMING CORE SYNC GENERATOR INTERNAL REGISTERS DOUT0P_A DOUT0N_A DOUT1P_A DOUT1N_A TCLKP_A TCLKN_A DOUT0P_B DOUT0N_B DOUT1P_B DOUT1N_B TCLKP_B TCLKN_B CLI_A CLI_B SCK_A SCK_B HL_A HL_B HD_A VD_A HD_B VD_B Figure 1. SL_A SDATA_A SL_B SDATA_B For more information about the AD9973, contact Analog Devices, Inc. via email at [email protected]. Rev. SpA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. 1 page

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