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PDF AD5392 Data sheet ( Hoja de datos )
| Número de pieza | AD5392 | |
| Descripción | 12-/14-Bit Voltage Output DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5392 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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8-/16-Channel, 3 V/5 V, Serial Input, Single-
Supply, 12-/14-Bit Voltage Output DACs
AD5390/AD5391/AD5392
FEATURES
INTEGRATED FUNCTIONS
AD5390: 16-channel, 14-bit voltage output DAC
Channel monitor
AD5391: 16-channel, 12-bit voltage output DAC
Simultaneous output update via LDAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
INL: ±1 LSB max (AD5391)
±3 LSB max (AD5390-5/AD5392-5)
±4 LSB max (AD5390-3/AD5392-3)
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
www.DTaetmaSpheeraettu4Ure.croamnge: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package types:
64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)
User interfaces:
Serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
(featuring data readback)
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Control systems
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)
I2C®-compatible interface
FUNCTIONAL BLOCK DIAGRAM
DVDD (×2)
DGND (×2)
AVDD (×2)
AGND (×2) DAC_GND (×2) REF_GND REFOUT/REFIN SIGNAL_GND (×2)
AD5390
1.25V/2.5V
REFERENCE
SPI/I2C
DCEN/AD1
DIN/SDA
SCLK/SCL
SYNC/AD0
SDO
BUSY
PD
CLR
RESET
MON_IN1
MON_IN2
INTERFACE
CONTROL
LOGIC
STATE
MACHINE
AND
CONTROL
LOGIC
POWER-ON
RESET
VIN0 VIN15
MUX
14 INPUT 14
REG
0
14 m REG0
14 c REG0
14 INPUT 14
REG
1
14 m REG1
14 c REG1
14 DAC 14
REG
0
DAC 0
14 DAC 14
REG
1
DAC 1
14 INPUT 14
REG
6
14 m REG6
14 c REG6
14 INPUT 14
REG
7
14 m REG7
14 c REG7
14 DAC 14
REG
6
DAC 6
14 DAC 14
REG
7
DAC 7
×2
RR
RR
RR
RR
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 15
MON_OUT
Figure 1.
LDAC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD5390/AD5391/AD5392
Parameter
LOGIC INPUTS (SCL, SDA Only)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
LOGIC OUTPUTS (BUSY, SDO)
2
Output Low Voltage
Output High Voltage
www.DatOauShtpeuettL4oUw.cVoomltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
LOGIC OUTPUT (SDA)
2
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity
2
∆Midscale/∆AVDD
AIDD
AIDD
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5390-5
1
AD5391-5
1
AD5392-51
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
8
50
0.7 DVDD
0.3 DVDD
±1
0.05 DVDD
8
50
0.4
DVDD − 1
0.4
DVDD − 0.5
±1
5
0.4
DVDD − 1
0.4
DVDD − 0.5
±1
5
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
−85
0.375
0.475
1
1
20
35
20
0.4
0.6
±1
8
4.5/5.5
2.7/5.5
−85
0.375
0.475
1
1
20
35
20
Unit
V min
V max
µA max
V min
pF typ
ns max
V max
V min
V max
V min
µA max
pF typ
V max
V max
µA max
pF typ
V min/max
V min/max
dB typ
mA/channel
max
mA/channel
max
mA max
µA max
µA max
mW max
mW max
Test Conditions/Comments
SMBus-compatible at DVDD < 3.6 V.
SMBus-compatible at DVDD < 3.6 V.
Input filtering suppresses noise spikes of
<50 ns.
DVDD = 5 V ± 10%, sinking 200 µA.
DVDD = 5 V ± 10%, SDO only, sourcing
200 µA.
DVDD = 2.7 V to 3.6 V, sinking 200 µA.
DVDD = 2.7 V to 3.6 V SDO only, sourcing
200 µA.
ISINK = 3 mA.
ISINK = 6 mA.
Outputs unloaded; boost off;
0.25 mA/channel typ.
Outputs unloaded; boost on;
0.325 mA/channel typ.
VIH = DVDD, VIL = DGND.
Typically 200 nA.
Typically 3 µA.
AD5390/AD5391 with outputs unloaded;
AVDD = DVDD = 5 V; boost off.
AD5392 with outputs unloaded;
AVDD = DVDD = 5 V, boost off.
1 AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.
2 Guaranteed by characterization, not production tested.
3 Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in
performance accuracy.
4 Accuracy guaranteed from VOUT = 10 mV to AVDD − 50 mV.
Rev. A | Page 5 of 44
5 Page 
SCLK
SYNC
DIN
SDO
www.DataSheet4U.coLDmAC
AD5390/AD5391/AD5392
t7
t4
DB23
t8
t9
t3
t1
24
t2
DB0 DB23
48
t21
t22
DB0
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N+1
t20
DB23
INPUT WORD FOR DAC N
DB0
t23
t13
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
SCLK
SYNC
DIN
12
t4
t7
t6
t8
DB23
t3
t9
t1
24
t2
t5
DB0
24
BUSY
LDAC1
VOUT1
LDAC2
VOUT2
CLR
VOUT
t18
t19
t10
t12
t11
t13
t17
t14
t15
t13
t17
t16
1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE DURING BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
Rev. A | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5392.PDF ] | |
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