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PDF HMD8M36M6G Data sheet ( Hoja de datos )
| Número de pieza | HMD8M36M6G | |
| Descripción | 32Mbyte(8Mx36) 72-pin SIMM FP | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMD8M36M6G
32Mbyte(8Mx36) 72-pin SIMM FP with Parity Mode, 4K Ref. 5V
Part No. HMD8M36M6, HMD8M36M6G
GENERAL DESCRIPTION
The HMD8M36M6 is a 8M x 36bit dynamic RAM high density memory module. The module consists of four CMOS 4M x
16 bit DRAMs in 50-pin TSOP packages and two CMOS 4M x 4bit Quad CAS DRAM in 28pin SOJ package mounted on a
72-pin, double-sided, FR-4-printed circuit board. A 0.1uF or 0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM components.
The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge
connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs
are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD8M36M6----4K Cycles/64ms Ref. Solder
HMD8M36M6G- 4K Cycles/64ms Ref. Gold
w Access times : 50, 60ns
w High-density 32MByte design
w Single +5V ± 0.5V power supply
w JEDEC Standard pinout
w Fast Page mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
MARKING
-5
-6
w Packages
72-pin SIMM
M
PRESENCE DETECT PINS
Pin 50ns
PD1
NC
PD2
Vss
PD3
Vss
PD4
Vss
60ns
NC
Vss
NC
NC
PERFORMANCE RANGE
Speed
tRAC
tCAC
5
50ns
13ns
6
60ns
15ns
tRC
90ns
110ns
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ24 49 DQ9
2
DQ0
26
DQ7
50 DQ27
3 DQ18 27 DQ25 51 DQ10
4
DQ1
28
A7
52 DQ28
5 DQ19 29 A11 53 DQ11
6
DQ2
30
Vcc
54 DQ29
7 DQ20 31 A8 55 DQ12
8
DQ3
32
A9
56 DQ30
9 DQ21 33 NC 57 DQ13
10 Vcc 34 NC 58 DQ31
11 NC 35 DQ26 59 Vcc
12 A0 36 DQ8 60 DQ32
13 A1 37 DQ17 61 DQ14
14 A2 38 DQ35 62 DQ33
15 A3 39 Vss 63 DQ15
16 A4 40 /CAS0 64 DQ34
17 A5 41 /CAS2 65 DQ16
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67 PD1
20 DQ4 44 /RAS0 68
PD2
21 DQ22 45 /RAS1 69
PD3
22 DQ5 46 NC 70 PD4
23 DQ23 47 /WE 71 NC
24 DQ6 48 NC 72 Vss
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-1-
HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD8M36M6G
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
10
10
ns
Column Address to /RAS lead time
tRAL 25 30 ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP 10 10 ns
Write command to /RAS lead time
www.DataSheWetr4itUe.ccoommmand to /CAS lead time
tRWL
15
15
ns
tCWL
13
15
ns
Data-in set-up time
tDS 0 0 ns
Data-in hold time
tDH 10 15 ns
Data-in hold referenced to /RAS
tDHR
50
55
ns
Refresh period
tREF 64 64 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA 30 35 Ns
Fast page mode cycle time
tPC 35 40 Ns
/CAS precharge time (Fast page)
tCP 10 10 ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
URL:www.hbe.co.kr
REV.1.0 (August.2002)
-5-
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HMD8M36M6G.PDF ] | |
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