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PDF HMD8M36M24EG Data sheet ( Hoja de datos )
| Número de pieza | HMD8M36M24EG | |
| Descripción | 32Mbyte(8Mx36) 72-pin EDO | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD8M36M24EG
32Mbyte(8Mx36) 72-pin EDO with ParityMODE 2K Ref. SIMM Design 5V
Part No. HMD8M36M24EG
GENERAL DESCRIPTION
The HMD8M36M24EG is a 8M x 36bit dynamic RAM high density memory module. The module consists of twenty four
CMOS 4M x 4bit DRAM in 24-pin SOJ packages mounted on a 72 -pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72 -pin edge connector sockets. All
module components may be powe red from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
www.DwaPtaaSrht eIdeet4nUti.fcicoamtion
HMD8M36M24E---- 2048 Cycles/32ms Ref. Solder
HMD8M36M24EG- 2048 Cycles/32ms Ref. Gold
w Access times : 50, 60ns
w High-density 32MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard PDpin and pinout
w EDO mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PRESENCE DETECT PINS
Pin 50ns
PD1 NC
PD2 Vss
PD3 Vss
PD4 Vss
60ns
NC
Vss
Vss
NC
PERFORMANCE RANGE
Speed
tRAC
tCAC
5
50ns
13ns
6
60ns
15ns
TRC
90ns
110ns
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ24 49 DQ9
2
DQ0
26
DQ7
50 DQ27
3 DQ18 27 DQ25 51 DQ10
4
DQ1
28
A7
52 DQ28
5 DQ19 29 A11 53 DQ11
6
DQ2
30
Vcc
54 DQ29
7 DQ20 31 A8 55 DQ12
8
DQ3
32
A9
56 DQ30
9 DQ21 33 NC 57 DQ13
10 Vcc 34 NC 58 DQ31
11 NC 35 DQ26 59 Vcc
12 A0 36 DQ8 60 DQ32
13 A1 37 DQ17 61 DQ14
14 A2 38 DQ35 62 DQ33
15 A3 39 Vss 63 DQ15
16 A4 40 /CAS0 64 DQ34
17 A5 41 /CAS2 65 DQ16
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67 PD1
20 DQ4 44 /RAS0 68
PD2
21 DQ22 45
/RAS1
69
PD3
22 DQ5 46 NC 70 PD4
23 DQ23 47
/WE
71
NC
24 DQ6 48 NC 72 Vss
SIMM TOP VIEW
tHPC
26ns
30ns
URL:www.hbe.co.kr
REV.1.0 (March.2004)
-1-
HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD8M36M24EG
Column address hold time
tCAH
8
10
ns
Column Address to /RAS lead time
Read command set-up time
tRAL
tRCS
25
0
30
0
ns
ns
Read command hold referenced to /CAS
Read command hold referenced to /RAS
tRCH
tRRH
0
0
0
0
ns
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
Write command pulse width
tWCR
tWP
50
10
55
10
ns
ns
Write command to /RAS lead time
Write command to /CAS lead time
tRWL
tCWL
13
8
10
10
ns
ns
Data-in set-up time
www.DataSheet4U.com
Data-in hold time
Refresh period
tDS
tDH
tREF
0
8
0
10
32
32
ns
ns
ns
Write command set-up time
/CAS setup time (C-B-R refresh)
tWCS
tCSR
0
5
0
5
ns
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
Access time from /CAS precharge
tRPC
tCPA
5
5
30
35
ns
ns
/CAS precharge time (Fast page)
/RAS pulse width (Fast page )
tCP
tRASP
8
50
200K
10
60
200K
ns
ns
/W to /RAS precharge time (C-B-R
refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If t RCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD ³ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit conditi on and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If t WCS ³ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read -
write cycles.
URL:www.hbe.co.kr
REV.1.0 (March.2004)
-5-
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMD8M36M24EG.PDF ] | |
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