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PDF HMD8M32M16 Data sheet ( Hoja de datos )
| Número de pieza | HMD8M32M16 | |
| Descripción | 32Mbyte(8Mx32) 72-pin F/P Mode | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD8M32M16
32Mbyte(8Mx32) 72-pin F/P Mode 2K Ref. SIMM Design 5V
Part No. HMD8M32M16, HMD8M32M16G
GENERAL DESCRIPTION
The HMD8M32M16 is a 8M x 32 bit dynamic RAM high density memory module. The module consists of sixteen CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD8M32M16--2048 Cycles/32ms Ref, Solder
HMD8M32M16G--2048 Cycles/32ms Ref, Gold
w Access times : 50, 60ns
w High-density 32MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w FP(Fast Page) mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PERFORMANCE RANGE
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 19 A10 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 Vss 57 DQ12
4 DQ1 22 DQ5 40 /CAS0 58 DQ28
5 DQ17 23 DQ21 41 /CAS2 59 Vcc
6 DQ2 24 DQ6 42 /CAS3 60 DQ29
7 DQ18 25 DQ22 43 /CAS1 61 DQ13
8 DQ3 26 DQ7 44 /RAS0 62 DQ30
9 DQ19 27 DQ23 45 /RAS1 63 DQ14
10 Vcc 28 A7 46 NC 64 DQ31
11 NC 29 NC(A11) 47 /W 65 DQ15
12 A0 30 Vcc 48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14 A2 32 A9 50 DQ24 68 PD2
15 A3 33 /RAS1 51 DQ9 69 PD3
16 A4 34 /RAS0 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 Vss
SPEED tRAC tCAC tRC
-5 50ns 13ns 90ns
-6 60ns
PIN NAMES
15ns 110ns
Pin Name
Function
A0-A10
Address Input(2K Ref)
A0-A11
Address Input(4K Ref)
DQ0-DQ31
Data In/Out
/W Read/Write Input
tPC
35ns
40ns
SIMM TOP VIEW
Note: A11 is not used for HMD8M32M16
Pin Name
Function
/RAS0, /RAS1 Row Address Strobe
/CAS0 - /CAS3 Column Address Strobe
PD1 - PD4
Presence Detect
Pin Name
Vss
NC
Vcc
Function
Ground
No Connection
Power(+5V)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD8M32M16
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
15
15
ns
Column address hold referenced to /RAS
tAR 50 55 ns
Column Address to /RAS lead time
tRAL 30 35 ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
www.DataSheWetr4itUe.ccoommmand hold referenced to /RAS
tWCH
15
15
ns
tWCR
50
55
ns
Write command pulse width
tWP 15 15 ns
Write command to /RAS lead time
tRWL
15
20
ns
Write command to /CAS lead time
tCWL
15
20
ns
Data-in set-up time
tDS 0 0 ns
Data-in hold time
tDH 15 15 ns
Data-in hold referenced to /RAS
tDHR
50
55
ns
Refresh period
tREF 16 16 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
10
10
ns
/CAS hold time (C-B-R refresh)
tCHR
15
15
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA 35 40 ns
Fast page mode cycle time
tPC 40 45 ns
/CAS precharge time (Fast page)
tCP 10 10 ns
/RAS pulse width (Fast page )
tRASP
60
100K 70
100K
ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
/CAS precharge(C-B-R counter test)
tCPT 20 30 ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
URL:www.hbe.co.kr
REV.1.0 (August.2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HMD8M32M16.PDF ] | |
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