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PDF HMD4M32M8GL Data sheet ( Hoja de datos )
| Número de pieza | HMD4M32M8GL | |
| Descripción | 16Mbyte(4Mx32) Fast Page Mode | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD4M32M8GL
16Mbyte(4Mx32) Fast Page Mode, 4K Refresh 72Pin SIMM
Part No. HMD4M32M8GL
GENERAL DESCRIPTION
The HMD4M32M8GL is a 4M x 32bit dynamic RAM high-density memory module. The module consists of eight CMOS
4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single
In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All
module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD4M32M8GL- 4,096 Cycles/64ms Ref . Gold
w Access times : 50, 60ns
w High-density 16MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w FP(Fast Page) mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
MARKING
-5
-6
M
PIN CONFIGURATION DESCRIPTION
Pin Name
A0 – A11
A0 – A10
FUNCTION
Address Input(4K Ref.)
Address Input(2K Ref.)
DQ0-31
Data In/Out
/WE0-/WE3
Read/Write Input
/OE Data Output Enable
/CAS
Column Address Strobe
/RAS
Row Address Strobe
BDIN
SIZE
Board Insertion Signal
Size Indentification
Vcc/ Vss
Power and Ground
NC No Connection
URL: www.hbe.co.kr
REV.1.0. (August. 2002)
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
Vss
25 DQ22
49
DQ8
2 DQ0 26 DQ7 50 DQ24
3 DQ16 27 DQ23 51
DQ9
4 DQ1 28
A8
52 DQ25
5 DQ17 29
A10
53 DQ10
6
DQ2
30
Vcc
54 DQ26
7 DQ18 31 /WE2 55 DQ11
8 DQ3 32
NC
56 DQ27
9 DQ19 33
Vss
57 DQ12
10 Vcc
34 /RAS
58 DQ28
11 /WE0
35
Vcc
59 /WE3
12 A0
36 NC
60 DQ29
13 A1
37 NC
61 DQ13
14 A2
38 /OE0
62 DQ30
15 A3
39 Vss
63 DQ14
16 A4
40 /CAS
64 DQ31
17 A5
41 Vcc
65 DQ15
18 A6
42 NC
66 Vss
19 A7 43 NC 67 NC
20 DQ4
44
NC
68
NC
21 DQ20
22 DQ5
45
46
A9
A11
69 BDIN
70 NC
23 DQ21 47 /WE1 71 SIZE
24 DQ6
48
Vcc
72
Vss
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD4M32M8GL
Column address hold time
tCAH
10
10
ns
Column address hold referenced to /RAS
tAR 40
45
ns
Column Address to /RAS lead time
tRAL 25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command hold referenced to /RAS
tWCR
40
45
ns
Write command pulse width
tWP 10
10
ns
Write command to /RAS lead time
w w w . D a t aWSrhiteeceotm4mUa.ncdotom/CAS lead time
tRWL
tCWL
15
13
15
15
ns
ns
Data-in set-up time
tDS 0
0
ns
Data-in hold time
tDH 10
15
ns
Data-in hold referenced to /RAS
tDHR
40
45
ns
Refresh period 2K Ref.
tREF 32 32 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA 30 35 ns
Fast page mode cycle time
tPC 35
40
ns
/CAS precharge time (Fast page)
tCP 10
10
ns
/RAS pulse width (Fast page )
tRASP 50 200K 60 200K
ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
/CAS precharge(C-B-R counter test)
tCPT 20
20
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
URL: www.hbe.co.kr
REV.1.0. (August. 2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
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| PDF Descargar | [ Datasheet HMD4M32M8GL.PDF ] | |
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