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PDF HMD4M32M2VE Data sheet ( Hoja de datos )
| Número de pieza | HMD4M32M2VE | |
| Descripción | 16Mbyte(4Mx32) DRAM SIMM EDO MODE | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMD4M32M2VE
16Mbyte(4Mx32) DRAM SIMM EDO MODE, 4K Refresh, 3.3V
Part No. HMD4M32M2VE, HMD4M32M2VEG
GENERAL DESCRIPTION
The HMD4M32M2VE is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of two CMOS
4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM components. The module is a single In-line memory module with edge
connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered
from a single 3.3V DC power supply. All inputs and outputs are LVTTL-compatible.
www.DataShFeEetA4UT.cUoRmES
w Part Identification
HMD4M32M2VE----Lead finish Solder
HMD4M32M2VEG- Lead finish Gold
w Access times : 50, 60ns
w High-density 16MByte design
w 4K Cycles/64ms Ref, Gold
w Single +3.3V± 0.3V power supply
wJEDEC standard pinout
w EDO Mode operation
w LVTTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
60ns access
w Packages
72-pin SIMM
-5
-6
M
PERFORMANCE RANGE
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 VSS 19 A10 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 VSS 57 DQ12
4 DQ1 22 DQ5 40 /CAS0 58 DQ28
5 DQ17 23 DQ21 41 /CAS2 59 VCC
6 DQ2 24 DQ6 42 /CAS3 60 DQ29
7 DQ18 25 DQ22 43 /CAS1 61 DQ13
8 DQ3 26 DQ7 44 /RAS0 62 DQ30
9 DQ19 27 DQ23 45 NC 63 DQ14
10 VCC 28 A7 46 NC 64 DQ31
11 NC 29 A11 47 /W 65 DQ15
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14
A2
32
A9
50 DQ24 68
PD2
15 A3 33 NC 51 DQ9 69 PD3
16 A4 34 NC 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 VSS
Speed
tRAC
tCAC
tRC
5
50ns
13ns
84ns
6 60ns
PIN NAMES
15ns
104ns
Pin Name
Function
Pin Name
Function
Pin Name
Function
A0-A11
Address Input(4K Ref) /RAS0
Row Address Strobe
Vss
Ground
DQ0-DQ31 Data In/Out
/CAS0 - /CAS3 Column Address Strobe
NC
No Connection
/W
Read/Write Input
PD1 - PD4
Presence Detect
Vcc Power(+3.3V)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1 H ANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD4M32M2VE
Column address hold time
tCAH
8
10 ns
Column Address to /RAS lead time
tRAL 25 30 ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP 10 10 ns
Write command to /RAS lead time
tRWL
10
10
ns
Write command to /CAS lead time
tCWL
8
10 ns
Data-in set-up time
www.DataSheDeat4taU-.icnohmold time
tDS 0
tDH 8
0 ns
10 ns
Refresh period
tREF 64 64 ns
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA 35 40 ns
Fast page mode cycle time
tPC 28 35 ns
/CAS precharge time (Fast page)
tCP 8
10 ns
/RAS pulse width (Fast page )
tRASP
50
100K 60
100K
ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5.Assumes that tRCD ≥ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read-
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
5 H ANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HMD4M32M2VE.PDF ] | |
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