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PDF HMD2M32M4E Data sheet ( Hoja de datos )
| Número de pieza | HMD2M32M4E | |
| Descripción | 8Mbyte(2Mx32) EDO Mode | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMD2M32M4E/4EG
8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design
Part No. HMD2M32M4E, HMD2M32M4EG
GENERAL DESCRIPTION
The HMD2M32M4E is a 2M x 32bit dynamic RAM high-density memory module. The module consists of four CMOS 1M
x 16bit DRAMs in 42-pin SOJ packages mounted on a 72 -pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF
decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In -line
Memory Module with edge connections and is intended for mounting in to 72 -pin edge connector sockets. All module
components may be powered from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
www.DwaPtaaSrht eIdeet4nUti.fcicoamtion
HMD2M32M4E---- 1024 Cycles/16ms Ref . Solder
HMD2M32M4EG- -1024 Cycles/16ms Ref . Gold
w Access times : 50, 60ns
w High-density 8MByte design
w Single + 5V ±0.5V power supply
w JEDEC standard pinout
w EDO mode operation
w TTL compatible inputs and outputs
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
-50
60ns access
-60
70ns access
-70
w Packages
72-pin SIMM
M
PERFORMANCE RANGE
Speed
tRAC
tCAC
5
50ns
15ns
6
60ns
15ns
7
70ns
15ns
PRESENCE DETECT PINS
tRC
90ns
110ns
130ns
Pin 50ns
PD1 NC
PD2 NC
PD3 Vss
PD4 Vss
60ns
NC
NC
NC
NC
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1 Vss 25 DQ22 49 DQ8
2
DQ0
26
DQ7
50 DQ24
3 DQ16 27 DQ23 51
DQ9
4
DQ1
28
A7
52 DQ25
5 DQ17 29 A11 53 DQ10
6
DQ2
30
Vcc
54 DQ26
7 DQ18 31 A8 55 DQ11
8
DQ3
32
A9
56 DQ27
9 DQ19 33 /RAS3 57 DQ12
10 Vcc 34 /RAS2 58 DQ28
11 NC 35 NC 59 Vcc
12 A0 36 NC 60 DQ29
13 A1 37 NC 61 DQ13
14 A2 38 NC 62 DQ30
15 A3 39 Vss 63 DQ14
16 A4 40 /CAS0 64 DQ31
17 A5 41 /CAS2 65 DQ15
18 A6 42 /CAS3 66 NC
19 A10 43 /CAS1 67 PD1
20 DQ4 44 /RAS0 68
PD2
21 DQ20 45
/RAS1
69
PD3
22 DQ5 46 NC 70 PD4
23 DQ21 47 /WE 71
NC
24 DQ6 48 NC 72 Vss
70ns
NC
NC
Vss
NC
URL:www.hbe.co.kr
REV.1.0 (August.2002)
6 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMD2M32M4E/4EG
Column address set-up time
tASC
0
0 ns
Column address hold time
tCAH
8
10 ns
Column Address to /RAS lead time
tRAL 25 30 ns
Read command set-up time
tRCS
0
0 ns
Read command hold referenced to /CAS
tRCH
0
0 ns
Read command hold referenced to /RAS
tRRH
0
0 ns
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP 10 10 ns
Write command to /RAS lead time
tRWL
13
15
ns
Write command to /CAS lead time
tCWL
13
15
ns
Data-in set-up time
www.DataSheet4U.com
Data-in hold time
tDS 0
tDH 8
0 ns
10 ns
Refresh period (1K Ref. Normal)
tREF 16 16 ms
Write command set-up time
tWCS
0
0 ns
/CAS setup time (C-B-R refresh)
tCSR
5
5 ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5 ns
Access time from /CAS precharge
tCPA 30 35 ns
/CAS precharge time (Fast page)
tCP 8
10 ns
/RAS pulse width (Fast page )
tRASP
50 200K 60 200K ns
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
NOTES
1.An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If t RCD
is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD ³ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as e lectrical characteristic only. If t WCS ³ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read -
write cycles.
11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference
point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by t AA.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
10 HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HMD2M32M4E.PDF ] | |
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