AD5570 Datasheet PDF - Analog Devices
| Part Number | AD5570 | |
| Description | Serial Input Voltage Output DAC | |
| Manufacturers | Analog Devices | |
| Logo |  |
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True Accuracy, 16-Bit ±12 V/±15 V,
Serial Input Voltage Output DAC
AD5570
FEATURES
Full 16-bit performance
1 LSB max INL and DNL
Output voltage range up to ±14 V
On-board reference buffers, eliminating the need for a
negative reference
Controlled output during power-on
Temperature range of −40°C to +85°C/−40°C to +125°C
Settling time of 10 µs to 0.003%
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Asynchronous update of outputs (LDAC pin)
Power-on reset
Serial data output for daisy chaining
Data readback facility
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
Data acquisition systems
General-purpose instrumentation
REFGND
REFIN
LDAC
FUNCTIONAL BLOCK DIAGRAM
VSS VDD DGND
AD5570
POWER-ON
RESET
R
16-BIT
R DAC
R
R
DAC REGISTER
VOUT
AGND
AGNDS
SHIFT REGISTER
POWER-DOWN
CONTROL LOGIC
PD
SDIN SCLK SYNC SDO
Figure 1.
CLR
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC
that operates from supply voltages of ±12 V up to ±15 V.
Integral linearity (INL) and differential nonlinearity (DNL) are
accurate to 1 LSB. During power-up (when the supply voltages
are changing), VOUT is clamped to 0 V via a low impedance path.
The AD5570 DAC comes complete with a set of reference
buffers. The reference buffers allow a single, positive reference
to be used. The voltage on REFIN is gained up and inverted
internally to give the positive and negative reference for the
DAC core. Having the reference buffers on-chip eliminates the
need for external components such as inverters, precision
amplifiers, and resistors, thereby reducing the overall solution
size and cost.
The AD5570 uses a versatile 3-wire interface that is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards.
Data is presented to the part in the format of a 16-bit serial
word. Serial data is available on the SDO pin for daisy-chaining
purposes. Data readback allows the user to read the contents of
the DAC register via the SDO pin.
Features on the AD5570 include LDAC, which may be used to
update the output of the DAC. The device also has a power-
down pin (PD), which allows the DAC to be put into a low
power state, and a CLR pin that allows the output to be cleared
to 0 V.
The AD5570 is available in a 16-lead SSOP package.
PRODUCT HIGHLIGHTS
1. 1 LSB maximum INL and DNL.
2. Buffered voltage output up to ±14 V.
3. Output controlled during power-up.
4. On-board reference buffers.
5. Wide temperature range of −40°C to +125°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
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AD5570
STANDALONE TIMING CHARACTERISTICS
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ;
and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN, TMAX
Unit
Description
fMAX 10
MHz max
SCLK frequency
t1 100
ns min
SCLK cycle time
t2 35
ns min
SCLK high time
t3 35
ns min
SCLK low time
t4 10
ns min
SYNC to SCLK falling edge setup time
t5 35
ns min
Data setup time
t6 0
ns min
Data hold time
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t8 45
ns min
ns min
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
t9 0
ns min
SYNC rising edge to LDAC falling edge
t10 50
ns min
LDAC pulse width
t11 0
ns min
LDAC falling edge to SYNC falling edge (no update)
t12 0
ns min
LDAC rising edge to SYNC rising edge (no update)
t13 20
ns min
CLR pulse width
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
SCLK
SYNC
SDIN
t8 t4
DB15
t6
t5
LDAC1
LDAC2
t11
t2
t1
t3
t7
DB0
t9
t10
t12
CLR
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
Figure 2. Serial Interface Timing Diagram
t13
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