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PDF 25AA010A Data sheet ( Hoja de datos )
| Número de pieza | 25AA010A | |
| Descripción | 1K SPI Bus Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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25AA010A/25LC010A
1K SPI Bus Serial EEPROM
Device Selection Table
Part Number
25AA010A
25LC010A
VCC Range
1.8-5.5V
2.5-5.5V
Page Size
16 Bytes
16 Bytes
Temp. Ranges
I
I, E
Packages
P, MS, SN, ST, MC, OT
P, MS, SN, ST, MC, OT
Features:
• 10 MHz max. Clock Frequency
• Low-Power CMOS Technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 μA at 5.5V
• 128 x 8-bit Organization
• Write Page mode (up to 16 bytes)
• Sequential Read
• Self-Timed Erase and Write Cycles (5 ms max.)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1,000,000 Erase/Write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Ranges Supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
• Pb-Free and RoHS Compliant
Pin Function Table
Name
Function
CS Chip Select Input
SO Serial Data Output
WP
VSS
SI
SCK
Write-Protect
Ground
Serial Data Input
Serial Clock Input
HOLD
VCC
Hold Input
Supply Voltage
Description:
The Microchip Technology Inc. 25XX010A* is a 1 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25XX010A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packages including 8-lead MSOP, 8-lead TSSOP and
rotated TSSOP, 8-lead 2x3 DFN, and 6-lead SOT-23.
Package Types (not to scale)
TSSOP/MSOP
(ST, MS)
PDIP/SOIC
(P, SN)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
SOT-23
(OT)
SCK
VSS
SI
1
2
3
6 VDD
5 CS
4 SO
DFN
(MC)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
X-Rotated TSSOP
(X/ST)
HOLD
VCC
CS
SO
1
2
3
4
8 SCK
7 SI
6 VSS
5 WP
*25XX010A is used in this document as a generic part number for the
25AA010A and the 25LC010A.
© 2008 Microchip Technology Inc.
DS21832E-page 1
1 page  
25AA010A/25LC010A
FIGURE 1-1:
CS
SCK
SO
SI
HOLD TIMING
17
16
n+2
n+1
18
n
n+2
n+1
n
17
16
19
High-Impedance
Don’t Care
n
5
n
HOLD
n-1
n-1
FIGURE 1-2:
SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
8
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
13
MSB out
Don’t Care
14
4
12
11
3
LSB in
3
15
ISB out
Mode 1,1
Mode 0,0
© 2008 Microchip Technology Inc.
DS21832E-page 5
5 Page 
25AA010A/25LC010A
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. See Figure 2-7 for the
WRSR timing sequence. Four levels of protection for the
array are selectable by writing to the appropriate bits in
the STATUS register. The user has the ability to write-
protect none, one, two or all four of the segments of the
array as shown in Table 2-3.
TABLE 2-3:
BP1
0
0
1
1
ARRAY PROTECTION
BP0
Array Addresses
Write-Protected
0 none
1 upper 1/4
(60h-7Fh)
0 upper 1/2
(40h-7Fh)
1 all
(00h-7Fh)
FIGURE 2-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Data to STATUS Register
0 00 00 0 01 7 6 54 3 2 10
High-Impedance
SO
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
© 2008 Microchip Technology Inc.
DS21832E-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25AA010A.PDF ] | |
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