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PDF PCA9509 Data sheet ( Hoja de datos )
| Número de pieza | PCA9509 | |
| Descripción | Level translating I2C-bus/SMBus repeater | |
| Fabricantes | NXP Semiconductors | |
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PCA9509
Level translating I2C-bus/SMBus repeater
Rev. 01 — 27 June 2006
Product data sheet
1. General description
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The PCA9509 is a level translating I2C-bus/SMBus repeater that enables processor low
voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retaining
all the operating modes and features of the I2C-bus system during the level shifts, it also
permits extension of the I2C-bus by providing bidirectional buffering for both the data
(SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximum
capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are over-voltage
tolerant and are high-impedance when the PCA9509 is unpowered.
The bus port B drivers are compliant with SMBus I/O levels, while port A uses a current
sensing mechanism to detect the input or output LOW signal which prevents bus lock-up.
Port A uses a 1 mA current source for pull-up and a 200 Ω pull-down driver. This results in
a LOW on the port A accommodating smaller voltage swings. The output pull-down on the
port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the
internal buffer is set about 50 mV lower than that of the output voltage LOW. When the
port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This
prevents a lock-up condition from occurring. The output pull-down on the port B drives a
hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level which
enables port B to connect to any other I2C-bus devices or buffer.
The PCA9509 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system
control. Caution should be observed to only change the state of the EN pin when the bus
is idle.
2. Features
I Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
I Voltage level translation from port A (1 V to VCC(B) − 1.0 V) to port B (3.0 V to 5.5 V)
I Requires no external pull-up resistors on lower voltage port A
I Active HIGH repeater enable input
I Open-drain inputs/outputs
I Lock-up free operation
I Supports arbitration and clock stretching across the repeater
I Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
I Powered-off high-impedance I2C-bus pins
I Operating supply voltage range of 1.0 V to VCC(B) − 1.0 V on port A, 3.0 V to 5.5 V on
port B
I 5 V tolerant port B SCL, SDA and enable pins
1 page  
Philips Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 1.1 V
I2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
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1.1 V
3.3 V
SDA
SCL
MASTER
CPU
1.1 V
10 kΩ
VCC(A)
10 kΩ
VCC(B)
A1
A2
PCA9509
B1
B2
EN
10 kΩ
SDA
SCL
SLAVE
400 kHz
bus A
bus B
002aac128
Fig 4. Typical application
When port B of the PCA9509 is pulled LOW by a driver on the I2C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3VCC(B) and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9509 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to Figure 5 and Figure 6. If the bus master in
Figure 4 were to write to the slave through the PCA9509, waveforms shown in Figure 5
would be observed on the B bus. This looks like a normal I2C-bus transmission.
On the A bus side of the PCA9509, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9509. After the 8th clock pulse, the data line will
be pulled to the VOL of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9509 for a short delay while the B bus side rises above 0.5VCC(B), then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the A bus side at the input of the PCA9509 (VIL) is below VILc to be
recognized by the PCA9509 and then transmitted to the B bus side.
SCL
9th clock pulse
acknowledge
SDA
PCA9509_1
Product data sheet
Fig 5. Bus B SMBus/I2C-bus waveform
Rev. 01 — 27 June 2006
002aab644
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 16
5 Page 
Philips Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
www.DataSheet4U.com
D
y
Z
8
c
5
EA
X
HE v M A
pin 1 index
1
e
A2
A1
4
bp
wM
Q
(A 3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(2) e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.024
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
SOT96-1
IEC
076E03
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 12. Package outline SOT96-1 (SO8)
PCA9509_1
Product data sheet
Rev. 01 — 27 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 16
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| Páginas | Total 16 Páginas | |
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