PDF ICS8430-111 Data sheet ( Hoja de datos )

Número de pieza	ICS8430-111
Descripción	LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION ICS The ICS8430-111 is a general purpose, dual out- put high frequency synthesizer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input lev- els. The single ended TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The VCO operates at a frequency range of 200MHz to 700MHz. With the output configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved www.DuastainSghaee1t64MU.Hczomdifferential or single ended reference clock. Out- put frequencies up to 700MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the ICS8430-111 makes it an ideal clock generator for most clock tree applications. FEATURES • Dual differential 3.3V LVPECL output • Selectable 14MHz to 27MHz differential CLK, nCLK or TEST_CLK input • CLK, nCLK accepts any differential input signal: LVPECL, LVHSTL, LVDS, SSTL, HCSL • TEST_CLK accepts the following input types: LVCMOS, LVTTL • Output frequency range up to 700MHz • VCO range: 200MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Industrial termperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL CLK_SEL TEST_CLK CLK nCLK MR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 0 1 ÷ 16 PLL PHASE DETECTOR VCO ÷M ÷2 0 ÷N 1 CONFIGURATION INTERFACE LOGIC FOUT0 nFOUT0 FOUT1 nFOUT1 32 31 30 29 28 27 26 25 M5 1 M6 2 M7 3 M8 4 N0 5 N1 6 N2 7 VEE 8 ICS8430-111 24 CLK 23 TEST_CLK 22 CLK_SEL 2 1 VCCA 20 S_LOAD 19 S_DATA 18 S_CLOCK 17 MR 9 10 11 12 13 14 15 16 TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8430DY-111 www.icst.com/products/hiperclocks.html REV. F JUNE 1, 2005 1 1 page Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. www.DataSheet4U.com TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Analog Voltage Ouput Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 120 10 Maximum 3.465 3.465 3.465 Units V V V mA mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol V IH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD M8, N2, CLK_SEL, VCO_SEL Input Low Current M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD M8, N2, CLK_SEL, VCO_SEL VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 NOTE 1: Outputs terminated with 50Ω to VCCO/2. Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V Minimum 2 -0.3 Typical Maximum V + 0.3 CC 0.8 Units V V 150 µA 5 µA -5 µA -150 2.6 µA V 0.5 V 8430DY-111 www.icst.com/products/hiperclocks.html 5 REV. F JUNE 1, 2005 5 Page Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show inter- face examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V www.DataSheet4U.com Zo = 50 Ohm Zo = 50 Ohm LVHSTL ICS HiPerClockS LVHSTL Driver 3.3V CLK nCLK HiPerClockS Input R1 R2 50 50 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm 3.3V CLK nCLK HiPerClockS Input R1 R2 50 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V Zo = 50 Ohm Zo = 50 Ohm LVPECL 3.3V R3 R4 125 125 3.3V CLK nCLK HiPerClockS Input R1 R2 84 84 3.3V LVDS_Driv er Zo = 50 Ohm Zo = 50 Ohm R1 100 3.3V CLK nCLK Receiv er FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V LVPECL 3.3V Zo = 50 Ohm Zo = 50 Ohm R3 R4 125 125 C1 C2 R5 100 - 200 R6 100 - 200 R1 R2 84 84 3.3V CLK nCLK HiPerClockS Input R5,R6 locate near the driver pin. FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 8430DY-111 www.icst.com/products/hiperclocks.html 11 REV. F JUNE 1, 2005 11 Page

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