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ICS86953I-147 fiches techniques PDF

Integrated Circuit Systems - 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

Numéro de référence ICS86953I-147
Description 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
Fabricant Integrated Circuit Systems 
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ICS86953I-147 fiche technique
Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
ICS
The ICS86953I-147 is a low voltage, low skew
1-to-9 Differential-to-LVCMOS/LVTTL Clock
HiPerClockS™ Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The PCLK, nPCLK pair can accept most stan-
dard differential input levels.With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with “zero delay”.
www.DataSheet4U.com
PIN ASSIGNMENT
FEATURES
• 9 single ended LVCMOS/LVTTL outputs;
(8) clocks, (1) feedback
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
• Maximum output frequency: PLL Mode, 175MHz
• VCO range: 250MHz to 700MHz
• Output skew: 75ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Static phase offset: 90ps ± 110ps
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC953
VDDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS86953I-147 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q1
VDDO
Q2
GND
Q3
VDDO
Q4
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
BLOCK DIAGRAM
PCLK
nPCLK
FB_CLK
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
86953BYI-147
Phase
Detector
LPF
VCO
0
1
0
÷2 1
0
÷4 1
www.icst.com/products/hiperclocks.html
1
QFB
/7 Q0:Q6
Q7
REV. B APRIL 23, 2004

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