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PDF ICS854054 Data sheet ( Hoja de datos )
| Número de pieza | ICS854054 | |
| Descripción | 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
GENERAL DESCRIPTION
The ICS854054 is a 4:1 Differential-to-LVDS Clock
ICS Multiplexer which can operate up to 2.8GHz and
HiPerClockS™ is a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS854054 has 4 selectable differential clock
inputs. The PCLK, nPCLK input pairs can accept LVPECL,
LVDS, CML or SSTL levels. The fully differential architec-
ture and low propagation delay make it ideal for use in clock
distribution circuits. The select pins have internal pulldown
resistors. The SEL1 pin is the most significant bit and the
www.DbaintaaSrhyeneut4mUb.ceor mapplied to the select pins will select the same
numbered data input (i.e., 00 selects PCLK0, nPCLK0).
FEATURES
• High speed 4:1 differential multiplexer
• One differential LVDS output
• Four selectable differential clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2.8GHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
• Part-to-part skew: 375ps (maximum)
• Propagation delay: 700ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
0 0(default)
01
10
11
PIN ASSIGNMENT
PCLK0 1
16 VDD
nPCLK0 2 15 Q
PCLK1 3 14 nQ
nPCLK1 4 13 GND
VDD 5
12 nPCLK3
SEL0 6 11 PCLK3
SEL1 7 10 nPCLK2
Q
GND 8
9 PCLK2
nQ
ICS854054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
SEL1 SEL0
854054AG
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 29, 2006
1 page  
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
www.DataSheet4U.com
0
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
-10
Additive Phase Jitter, RMS
-20 @ 155.52MHz (12kHz - 20MHz) = <0.195ps typical
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
854054AG
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 29, 2006
5 Page 
Integrated
Circuit
Systems, Inc.
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
www.DataSheet4U.com
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854054 is: 361
854054AG
www.icst.com/products/hiperclocks.html
11
REV. A MARCH 29, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS854054.PDF ] | |
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