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Integrated Circuit Systems - 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Numéro de référence ICS8745B
Description 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Fabricant Integrated Circuit Systems 
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ICS8745B fiche technique
Integrated
Circuit
Systems, Inc.
ICS8745Bwww.DataSheet4U.com
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
ICS
The ICS8745B is a highly versatile 1:5 LVDS Clock 5 differential LVDS outputs designed to meet
Generator and a member of the HiPerClockS™ or exceed the requirements of ANSI TIA/EIA-644
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS8745B has a fully integrated PLL
Selectable differential clock inputs
and can be configured as zero delay buffer, multi- CLKx, nCLKx pairs can accept the following differential
plier or divider, and has an output frequency range of 31.25MHz input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
to 700MHz. The Reference Divider, Feedback Divider and
Output Divider are each programmable, thereby allowing for
Output frequency range: 31.25MHz to 700MHz
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, Input frequency range: 31.25MHz to 700MHz
1:2, 1:4, 1:8.The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. VCO range: 250MHz to 700MHz
The PLL_SEL pin can be used to bypass the PLL for system External feedback for “zero delay” clock regeneration
test and debug purposes. In bypass mode, the reference clock with configurable frequencies
is routed around the PLL and into the internal output dividers.
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: 25ps ± 125ps
3.3V supply voltage
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
SEL1
SEL2
SEL3
MR
8745BY
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
0
Q2 32 31 30 29 28 27 26 25
nQ2
1 SEL0 1
24 Q3
Q3
nQ3
Q4
nQ4
SEL1
CLK0
nCLK0
CLK1
2
3
4
5
ICS8745B
23 nQ3
22 VDDO
21 Q2
20 nQ2
nCLK1 6
19 GND
CLK_SEL 7
18 Q1
MR 8
17 nQ1
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B DECEMBER 2, 2004

PagesPages 15
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