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PDF W3HG264M72EER-AD7 Data sheet ( Hoja de datos )
| Número de pieza | W3HG264M72EER-AD7 | |
| Descripción | 1GB - 2x64Mx72 DDR2 SDRAM REGISTERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4UA.cDoVmANCED*
1GB – 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL,
VLP Mini-DIMM
FEATURES
244-pin, very low profile dual in-line memory
module (VLP Mini-DIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300*, and PC2-6400*
Supports ECC error detection and correction
VCC = VCCQ = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Programmable CAS# latency (CL)
Posted CAS# additive latency (AL)
On-die termination (ODT)
Programmable burst lenghts: 4 or 8
Serial Presence Detect (SPD) with EEPROM
Auto and Self Refresh Capability (64ms: 8,192
cycle refresh)
Gold (Au) edge contacts
RoHS compliant
Dual Rank
Package option
• 244 Pin Mini-DIMM
• PCB – 18.29mm (0.72")
DESCRIPTION
The W3HG264M72EER is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity option
Clock Speed
CL-tRCD-tRP
* Contact factory for availability
PC2-3200
200MHz
3-3-3
OPERATING FREQUENCIES
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
December 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4U.AcDomVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature
TOPER
0°C to 85°C
°C
V
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
Parameter
Input High (Logic 1 ) Voltage
Input Low (Logic 0) Voltage
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 125
-300
Max
VREF + 300
VREF - 125
Unit
mV
mV
Parameter
AC Input High (Logic 1 ) Voltage (DDR2-400/533)
AC Input High (Logic 1) Voltage (DDR2-667)
AC Input Low (Logic 0) Voltage
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Symbol
Min
VIH(AC)
VIH(AC)
VIL(AC)
VREF + 250
VREF + 200
—
Max
—
VREF - 250
Unit
mV
mV
mV
December 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3HG264M72EER-AD7
www.DataSheet4U.AcDomVANCED
26. ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
high impedance. Both are measured from tAOFD.
27. This parameter has a two clock minimum requirement at any tCK.
28. tDELAY is calculated from tIS + tCK + tIH so that CKE registration
LOW is guaranteed prior to CK, CK# being removed in a system
RESET condition.
29. tISXR is equal to tIS and is used for CKE setup time during self
refresh exit.
30. No more than 4 bank ACTIVE commands may be issued in
a given tFAW (MIN) period. tRRRD (MIN) restriction still applies.
The tFAW (MIN) parameter applies to all 8 bank DDR2 devices,
regardless of the number of banks already open or closed.
31. tRPA timing applies when the PRECHARGE(ALL) command is
issued, regardless of the number of banks already open or closed.
If a single-bank PRECHARGE command is issued, tRP timing
applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
32. Value is minimum pulse width, not the number of clock
registrations.
33. Applicable to Read cycles only. Write cycles generally require
additional time due to Write recovery time (tWR) during arto
precharge.
34. tCKE (MIN) of 3 clocks means CKE must be registered on three
consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of
registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2* tCK + tIH.
35. This parameter is not referenced to a specific voltage level, but
specified when the device output is no longer driving (tRPST) or
beginning to drive (tRPRE).
36. When DQS is used single-ended, the minimum limit is reduced by
100ps.
December 2005
Rev. 0
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet W3HG264M72EER-AD7.PDF ] | |
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