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Número de pieza | M41T81S | |
Descripción | Serial access real-time clock | |
Fabricantes | STMicroelectronics | |
Logotipo | ||
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M41T81S
Serial access real-time clock with alarms
Features
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ 32KHz crystal oscillator with integrated load
capacitance (12.5pf) which provides
exceptional oscillator stability and high crystal
series resistance operation)
■ Oscillator stop detection (monitors clock
operation)
■ Serial interface supports i2c bus (400kHz
protocol)
■ Ultra-low battery supply current of 0.6μA (typ)
■ 2.0 to 5.5v clock operating voltage
■ Automatic switchover and deselect circuitry
(fixed reference) which provides full operation
in 3.0V applications)
■ VCC = 2.7 to 5.5V
■ 2.5V ≤ VPFD ≤ 2.7V
■ Power-down time stamp (ht bit) which allows
determination of time elapsed in battery back-
up
■ Battery low flag
■ Programmable alarm and interrupt function
(valid even during battery back-up mode)
■ Accurate programmable watchdog timer (from
62.5ms to 128s)
■ Software clock calibration (to compensate for
crystal deviation due to temperature)
■ Operating temperature of –40 to 85°C
■ Package options include an 8-lead SOIC or 18-
lead embedded crystal SOIC
8
1
SO8 (M)
8-pin SOIC
18
1
SOX18 (MY)
18-pin (300mil) SOIC
with Embedded Crystal
January 2007
Rev 5
1/31
www.st.com
1
1 page M41T81S
List of figures
List of figures
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Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
18-pin, 300mil SOIC (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SOx18 – 18-lead plastic small outline, 300mils, embedded crystal, outline . . . . . . . . . . . . 28
5/31
5 Page M41T81S
Figure 5. Serial bus data transfer sequence
CLOCK
DATA
START
CONDITION
DATA LINE
STABLE
DATA VALID
CHANGE OF
DATA ALLOWED
Operation
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STOP
CONDITION
AI00587
Figure 6. Acknowledgement sequence
SCL FROM
MASTER
START
1
DATA OUTPUT
BY TRANSMITTER
MSB
DATA OUTPUT
BY RECEIVER
2
CLOCK PULSE FOR
ACKNOWLEDGEMENT
89
LSB
AI00601
READ mode
Note:
In this mode the master reads the M41T81S slave after setting the slave address (see
Figure 8 on page 12). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge
Bit, the word address 'An' is written to the on-chip address pointer. Next the START
condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1).
At this point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an Acknowledge Bit to the
slave transmitter. The address pointer is only incremented on reception of an Acknowledge
Clock. The M41T81S slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a Stop Condition or when the
pointer increments to any non-clock address (08h-13h).
This is true both in READ Mode and WRITE Mode.
11/31
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet M41T81S.PDF ] |
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