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PDF EMIF07-LCD02F3 Data sheet ( Hoja de datos )

Número de pieza EMIF07-LCD02F3
Descripción EMI filter and ESD protection
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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EMIF07-LCD02F3
7-line IPAD™, EMI filter and ESD protection for LCD and cameras
Features
EMI symmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Lead-free package
Very low PCB space occupation:
1.42 mm x 1.42 mm
Very thin package: 0.65 mm
High efficiency in ESD suppression
High reliability offered by monolithic integration
High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards
IEC61000-4-2 level 4 on inputs and outputs:
– 15 kV (air discharge)
– 8 kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3
Applications
Where EMI filtering in ESD sensitive equipment is
required:
LCD for mobile phones
Computers and printers
Communication systems
MCU boards
Description
The EMIF07-LCD02F3 is a 7-line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The EMIF07 Flip Chip packaging
means the package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the protected device when
subjected to ESD surges up 15 kV.
Flip Chip
(18 bumps)
Figure 1. Pin layout (bump side)
54321
O1 O2 GND I1 I2 A
O3 GND
I3 B
O4 O5 GND I4 I5 C
O6 O7 GND I6 I7 D
Figure 2. Device configuration
Input
Low-pass Filter
Output
GND
GND
GND
Ri/o = 70
Cline = 30 pF
April 2008
TM: IPAD is a trademark of STMicroelectronics.
Rev 2
1/8
www.st.com
8

1 page




EMIF07-LCD02F3 pdf
EMIF07-LCD02F3
3 Ordering information scheme
Figure 10. Ordering information scheme
Ordering infworwmwa.DtiaotanSshecehte4Um.ceom
EMIF yy - xxx zz F3
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
3 = Lead-free, pitch = 400 µm, bump = 255 µm
4 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 11. Package dimensions
400 µm ± 40
255 µm± 40
605 µm ± 55
185 µm
1.97 mm ± 30µm
5/8

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