PDF HYB18T512161B2F-25 Data sheet ( Hoja de datos )

Número de pieza	HYB18T512161B2F-25
Descripción	512-Mbit x16 DDR2 SDRAM
Fabricantes	Qimonda AG
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No Preview Available ! June 2007 www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.1 1 page 2 Configuration Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM 2.1 Chip Configuration The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1. Ball# Clock Signals J8 K8 K2 Control Signals K7 L7 K3 L8 Address Signals Name Ball Type Buffer Type Function TABLE 2 Chip Configuration of DDR2 SDRAM CK I CK I CKE I RAS CAS WE CS I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL Clock Signal CK, Complementary Clock Signal CK Note: CK and CK are differential system clock inputs. All address and control inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossing of CK and CK (both direction of crossing) Clock Enable Note: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power- Down (row Active in any bank). CKE is synchronous for power down entry and exit and for self-refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is used asynchronously to detect self-refresh exit condition. Self-refresh termination itself is synchronous. After VREF has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 5 5 Page Internet Data Sheet www.DataSheet4U.com HYB18T512161B2F–20/25 512-Mbit Double-Data-Rate-Two SDRAM Field Bits Type1) Description BT 3 w BL [2:0] w Burst Type 0B BT Sequential 1B BT Interleaved Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8 1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN. %$%$$$$$$$$$$$$$$ 4RII '462&'3URJUDP5WW $/ 5WW',&'// UHJDGGU Z Z Z Z ZZZ Field BA1 BA0 Qoff Bits Type1) 14 reg. addr. 13 12 w DQS 10 OCD [9:7] Program TABLE 7 Extended Mode Register Definition (BA[1:0] = 01B) Description Bank Address [1] 0B BA1 Bank Address Bank Address [0] 1B BA0 Bank Address Output Disable 0B QOff Output buffers enabled 1B QOff Output buffers disabled Complement Data Strobe (DQS Output) 0B DQS Enable 1B DQS Disable Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default Rev. 1.1, 2007-06 05152007-ZYAH-ACMZ 11 11 Page

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