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PDF ADS8370 Data sheet ( Hoja de datos )
| Número de pieza | ADS8370 | |
| Descripción | MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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BurrĆBrown Products
from Texas Instruments
ADS8370
SLAS450 – JUNE 2005
16-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE
FEATURES
• 600-kHz Sample Rate
• ±0.5 LSB Typ, ±1.25 LSB Max INL
• ±0.4 LSB Typ, ±0.75 LSB Max DNL
• 16-Bit NMC
• SINAD 89.5 dB, SFDR 119 dB at fi = 1 kHz
• High-Speed Serial Interface up to 40 MHz
• Onboard Reference Buffer
• Onboard 4.096-V Reference
• Pseudo-Differential Input, 0 V to 4.2 V
• Onboard Conversion Clock
• Selectable Output Format, 2's Complement or
Straight Binary
• Zero Latency
• Wide Digital Supply
• Low Power:
– 110 mW at 600 kHz
– 15 mW During Nap Mode
– 10 µW During Power Down
• 28-Pin 6 x 6 QFN Package
• Pin compatible With 18-Bit ADS8380
APPLICATIONS
• Medical Instruments
• Optical Networking
• Transducer Interface
• High Accuracy Data Acquisition Systems
• Magnetometers
DESCRIPTION
The ADS8370 is a high performance 16-bit, 600-kHz
A/D converter with single-ended (pseudo-differential)
input. The device includes an 16-bit capacitor-based
SAR A/D converter with inherent sample and hold.
The ADS8370 offers a high-speed CMOS serial
interface with clock speeds up to 40 MHz.
The ADS8370 is available in a 28 lead 6 × 6 QFN
package and is characterized over the industrial
–40°C to 85°C temperature range.
Type/Speed
18-Bit Pseudo-Diff
500 kHz
ADS8383
18-Bit Pseudo-Bipolar, Fully Diff
16-Bit Pseudo-Diff
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
High Speed SAR Converter Family
~ 600 kHz
750 kHZ
ADS8381
ADS8380 (S)
ADS8382 (S)
ADS8370 (S) ADS8371
ADS8372 (S)
1 MHz
ADS7886
1.25 MHz
2 MHz
ADS8401/05 ADS8411
ADS8402/06 ADS8412
ADS7890 (S)
3 MHz
ADS7891
4 MHz
ADS7881
REFOUT
SAR
+IN
−IN
REFIN
+
_ CDAC
4.096-V
Internal
Reference
Comparator
Clock
Output
Latches
and
3-State
Drivers
Conversion
and
Control Logic
FS
SCLK
SB/2C
SDO
CS
CONVST
BUSY
PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the enmdoocf.tUh4istedeahtaSashtaeDet.www
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
1 page  
ADS8370
www.ti.com
TIMING REQUIREMENTS(1)(2)(3)(4)(5)(6)
SLAS450 – JUNE 2005
PARAMETER
tconv Conversion time
tacq1 Acquisition time in normal mode
tacq2 Acquisition time in nap mode (tacq2 = tacq1 + td18)
CONVERSION AND SAMPLING
tquiet1
Quite sampling time (last toggle of interface signals to convert start
command) (6)
tquiet2
Quite sampling time (convert start command to first toggle of interface
signals) (6)
tquiet3 Quite conversion time (last toggle of interface signals to fall of BUSY)(6)
tsu1 Setup time, CONVST before BUSY fall
tsu2 Setup time, CS before BUSY fall (only for conversion/sampling control)
tsu4 Setup time, CONVST before CS rise (so CONVST can be recognized)
th1 Hold time, CS after BUSY fall (only for conversion/sampling control)
th3 Hold time, CONVST after CS rise
th4 Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)(4)
tw1 CONVST pulse duration
tw2 CS pulse duration
tw5
Pulse duration, time between conversion start command and conversion
abort command to successfully abort the ongoing conversion
DATA READ OPERATION
tcyc SCLK period
SCLK duty cycle
tsu5 Setup time, CS fall before first SCLK fall
tsu6 Setup time, CS fall before FS rise
tsu7 Setup time, FS fall before first SCLK fall
th5 Hold time, CS fall after SCLK fall
th6 Hold time, FS fall after SCLK fall
tsu2 Setup time, CS fall before BUSY fall (only for read control)
tsu3 Setup time, FS fall before BUSY fall (only for read control)
th2 Hold time, CS fall after BUSY fall (only for read control)
th8 Hold time, FS fall after BUSY fall (only for read control)
tw2 CS pulse duration
tw3 FS pulse duration
MISCELLANEOUS
tw4 PD pulse duration for reset and power down
All unspecified pulse durations
ADS8370I/ADS8370IB
MIN TYP MAX
1000
1160
0.5
0.8
UNIT
ns
µs
µs
REF
FIGURE
41 – 44
41,42,44
43
30
ns
40 – 43,
45 – 47
10
ns
40 – 43,
45 – 47
600
ns
40 – 43,
45,47
15 ns 41
20 ns 40,41
5 ns 41,43,44
0 ns 41
7 ns 43
20 ns 42
20 ns 43
10 ns 41,42
1000 ns
44
25
40%
10
7
7
3
7
20
20
15
15
10
10
60
10
60%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45 – 47
45
46,47
46,47
45
46,47
40,45
40,47
40,45
40,47
45
46,47
53,54
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3) All digital output signals loaded with 10-pF capacitors.
(4) CONVST_QUAL is CONVST latched by a low value on CS (see Figure 39).
(5) Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.
(6) Quiet time zones are for meeting performance and not functionality.
moc.U4teehSataD.www
5
5 Page 
www.ti.com
TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
REFERENCE VOLTAGE
1
+VA = 5 V,
0.8 +VBD = 5 V,
0.6 TA = 25°C
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
2.5
3 3.5 4
Vref − Reference Voltage − V
Figure 18.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
2
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
1
0
−1
−2
−40 −25 −10 5 20 35 50 65 80
TA − Free-Air-Temperature − 5C
Figure 20.
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
1
0.75
0.5
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
0.25
0
−0.25
−0.5
−0.75
−1
−40 −25 −10 5 20 35 50 65
TA − Free-Air-Temperature − 5C
80
Figure 22.
ADS8370
SLAS450 – JUNE 2005
GAIN ERROR
vs
ANALOG SUPPLY VOLTAGE
6
4
2
0
−2
+VBD = 5 V,
REFIN = 4.096 V,
−4 TA = 25°C
−6
4.75
5
+VA − Analog Supply Voltage − V
5.25
Figure 19.
OFFSET ERROR
vs
REFERENCE VOLTAGE
1
0.75
0.5
+VA = 5 V,
+VBD = 5 V,
TA = 25°C
0.25
0
−0.25
−0.5
−0.75
−1
2.5
3 3.5
Vref − Reference Voltage − V
4
Figure 21.
OFFSET ERROR
vs
SUPPLY VOLTAGE
0.2
+VBD = 5 V,
0.1 REFIN = 4.096 V,
TA = 25°C
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
4.75 5
+VA − Analog Supply Voltage − V
Figure 23.
5.25
moc.U4teehSataD.www
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| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADS8370.PDF ] | |
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