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PDF R5F61525 Data sheet ( Hoja de datos )
| Número de pieza | R5F61525 | |
| Descripción | 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0104-0300
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The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
H8SX/1520Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer
H8SX Family H8SX/1500 Series
H8SX/1527
H8SX/1525
R5F61527
R5F61525
Rev.3.00
Revision Date: Mar. 14, 2006
1 page  
Configuration of This Manual
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This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 Mar. 14, 2006 Page v of xxxviii
5 Page 
4.6 Interrupts.............................................................................................................................. 81
4.6.1 Interrupt Sources.........................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 81
4.6.2 Interrupt Exception Handling ................................................................................. 82
4.7 Instruction Exception Handling ........................................................................................... 83
4.7.1 Trap Instruction....................................................................................................... 83
4.7.2 Exception Handling by Illegal Instruction .............................................................. 84
4.8 Stack Status after Exception Handling................................................................................. 85
4.9 Usage Note........................................................................................................................... 86
Section 5 Interrupt Controller ..............................................................................87
5.1 Features................................................................................................................................ 87
5.2 Input/Output Pins ................................................................................................................. 88
5.3 Register Descriptions ........................................................................................................... 89
5.3.1 Interrupt Control Register (INTCR) ....................................................................... 89
5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 90
5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R
(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) ....................................... 92
5.3.4 IRQ Enable Register (IER) ..................................................................................... 94
5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 96
5.3.6 IRQ Status Register (ISR)..................................................................................... 101
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 102
5.4 Interrupt Sources................................................................................................................ 103
5.4.1 External Interrupts ................................................................................................ 103
5.4.2 Internal Interrupts ................................................................................................. 104
5.5 Interrupt Exception Handling Vector Table....................................................................... 105
5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 112
5.6.1 Interrupt Control Mode 0 ...................................................................................... 112
5.6.2 Interrupt Control Mode 2 ...................................................................................... 114
5.6.3 Interrupt Exception Handling Sequence ............................................................... 116
5.6.4 Interrupt Response Times ..................................................................................... 117
5.6.5 DMAC Activation by Interrupt............................................................................. 118
5.7 CPU Priority Control Function Over DMAC .................................................................... 120
5.8 Usage Notes ....................................................................................................................... 122
5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 122
5.8.2 Instructions that Disable Interrupts ....................................................................... 123
5.8.3 Times when Interrupts are Disabled ..................................................................... 123
5.8.4 Interrupts during Execution of EEPMOV Instruction........................................... 123
5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123
5.8.6 Interrupt Flags of Peripheral Modules .................................................................. 124
Rev. 3.00 Mar. 14, 2006 Page xi of xxxviii
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