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PDF UPD160061 Data sheet ( Hoja de datos )
| Número de pieza | UPD160061 | |
| Descripción | 384-OUTPUT TFT-LCD SOURCE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
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µPD160061
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µPD160061 is a source driver for TFT-LCD’s capable of dealing with displays with 64-gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by
output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output
dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when
mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins
and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of
65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 384 outputs
• Input of 6 bits (gray-scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
• Logic power supply voltage (VDD1): 2.3 to 3.6 V
• Driver power supply voltage (VDD2): 7.5 to 9.5 V
• High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)
40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V)
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Input data inversion function (capable of controlling by each input port) (POL21, POL22)
• Apply for heavy load, light load
• Semi slim-chip shaped
ORDERING INFORMATION
Part Number
µPD160061N-xxx
µPD160061NL-xxx
Package
TCP (TAB package)
COF (COF package)
Remark The TCP’s/COF’s external shape are customized. To order the required shape, so please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15843EJ3V0DS00 (3rd edition)
Date Published June 2004 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2002
1 page  
µPD160061
Pin Symbol
Pin Name
SRC
High driving time
control
V0 to V9
γ -corrected power
supplies
VDD1
VDD2
VSS1
VSS2
Logic power supply
Driver power supply
Logic ground
Driver ground
I/O
Input
−
−
−
−
−
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Description
This pin is set up to high drive time of the output amplifier. Please decide the pin setting refer
to panel loads and one horizontal period. SRC pin is pulled up to the VDD1 inside the IC.
SRC = H or open: High drive time 64 CLK (Normally period mode)
SRC = L: High drive time 128 CLK (Long time mode)
Refer to 9. SRC AND HIGH DRIVE TIME.
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage output, be
sure to keep the gray scale level power supply at a constant level.
VDD2 − 0.2 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2
VDD2 − 0.3 V ≥ > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.2 V
2.3 to 3.6 V
7.5 to 9.5 V
Grounding
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power
supply terminals (V0, V1, V2,....., V9) and VSS.
Data Sheet S15843EJ3V0DS
5
5 Page 
µPD160061
8. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
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When the STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization
with the falling edge of STB.
Therefore, high drive time of the output amplifier as below is determined by the CLK number of the required SRC pin
setting. Be sure to avoid using such as extremely changing the CLK frequency (ex. CLK stop).
STB
Inside bias current
High drive time
High drive time
High drive time
POL
Vx (odd output)
V0 - V4
V5 - V9
V5 - V9
Vx (even output)
V5 - V9
V0 - V4
V0 - V4
Hi-Z
9. SRC AND HIGH DRIVE TIME
Hi-Z
Hi-Z
The µPD160061 can control high drive time of the output amplifier by SRC pin logic (refer to below figure).
SRC = H or open (high drive time: standard mode): High drive time (PWhp) of the output amplifier is in 64 CLK
period from falling edge of the STB.
SRC = L (high drive time: long-term mode): High drive time (PWhp) of the output amplifier is in 128 CLK period
from falling edge of the STB.
STB
CLK
Inside bias current
PWhp
We recommend a thorough simulation of the output amplifier in advance when set the SRC pin.
Data Sheet S15843EJ3V0DS
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet UPD160061.PDF ] | |
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