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PDF M58LR128GT Data sheet ( Hoja de datos )
| Número de pieza | M58LR128GT | |
| Descripción | 128 Mbit (8Mb x16- Multiple Bank Multi-Level - Burst) 1.8V Supply Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M58LR128GT
M58LR128GB
128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst)
1.8V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
– VDD = 1.7V to 2.0V for program, erase and
read
– VDDQ = 1.7V to 2.0V for I/O Buffers
– VPP = 9V for fast program (12V tolerant)
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array: 8 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Package
FBGA
VFBGA56 (ZB)
7.7 x 9mm
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code,
M58LR128GT: 88C4h.
– Bottom Device Code,
M58LR128GB: 88C5h.
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
June 2005
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M58LR128GT, M58LR128GB
Table 27. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19.VFBGA56 - 7.7 x 9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . . 56
Table 28. VFBGA56 - 7.7 x 9mm - 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . 56
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 30. M58LR128GT - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 31. M58LR128GT - Main Bank Base Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 32. M58LR128GT - Block Addresses in Main Banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 33. M58LR128GB - Parameter Bank Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 34. M58LR128GB - Main Bank Base Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 35. M58LR128GB - Block Addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 39. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 40. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 41. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 42. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 43. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 44. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 20.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 21.Buffer Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27.Buffer Enhanced Factory Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . 77
APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 46. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 47. Command Interface States - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 48. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 49. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 82
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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M58LR128GT, M58LR128GB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable input
controls data outputs during the Bus Read opera-
tion of the memory.
Write Enable (W). The Write Enable input con-
trols the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 16., Lock Status).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current IDD2. Refer to
Table 21., DC Characteristics - Currents, for the
value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 22., DC Characteristics - Voltages).
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
VIL and it is inhibited when Latch Enable is at
VIH. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write op-
erations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at VIH, Output Enable is
at VIH, or Reset is at VIL. It can be configured to be
active during the wait cycle or one data cycle in ad-
vance.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently of VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ)
VPP is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while VPP in the VPP1
range enables these functions (see Tables 21 and
22, DC Characteristics for the relevant values).
VPP is only sampled at the beginning of a program
or erase; a change in its value after the operation
has started does not have any effect and program
or erase operations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable un-
til the Program/Erase algorithm is completed.
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| PDF Descargar | [ Datasheet M58LR128GT.PDF ] | |
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