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PDF AD7680 Data sheet ( Hoja de datos )
| Número de pieza | AD7680 | |
| Descripción | 3mW + 100kSPS - 16-Bit ADC in 6 Lead SOT-23 | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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PRELIMINARY TECHNICAL DATA
a
3mW, 100kSPS,
www.DataSheet4U.com
16-Bit ADC in 6 Lead SOT-23
Preliminary Technical Data
AD7680
FEATURES
Fast Throughput Rate: 100kSPS
Specified for VDD of 2.5 V to 5.25 V
Low Power:
2.5mW typ at 100kSPS with 3V Supplies
15mW typ at 100kSPS with 5V Supplies
Wide Input Bandwidth:
85dB SNR at 10kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/µWire/DSP Compatible
Standby Mode: 0.5 µA max
6-Lead SOT-23, and 8-Lead MSOP Packages
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Remote Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7680 is a 16-bit, fast, low power, successive-ap-
proximation ADC. The part operates from a single 2.5 V
to 5.25 V power supply and features throughput rates up
to 100kSPS. The part contains a low-noise, wide band-
width track/hold amplifier which can handle input fre-
quencies in excess of 100kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7860 uses advanced design techniques to achieve
very low-power dissipation at fast throughput rates.
The reference for the part is taken internally from VDD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to VDD. The
conversion rate is determined by the SCLK frequency.
FUNCTIONAL BLOCK DIAGRAM
VDD
16-BIT SUCCESSIVE
VIN T/H APPROXIMATION
ADC
AD7680
CONTROL LOGIC
SCLK
SDATA
+5
GND
PRODUCT HIGHLIGHTS
1. First 16-Bit ADC in a SOT-23 package.
2. High Throughput with Low Power Consumption
3. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. This allows the average power
consumption to be reduced when a powerdown mode is
used while not converting. The part also features a shut-
down mode to maximize power efficiency at lower
throughput rates. Power consumption is 0.5µA max
when in shutdown.
4. Reference derived from the power supply.
5. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the sampling instant via a
CS input and once off conversion control.
REV. PrE 11/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
1 page  
PRELIMINARY TECHNICAL DATA
AD7680www.DataSheet4U.com
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full
scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 1LSB
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., VREF – 1
LSB) after the offset error has been adjusted out.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7860, it
is defined as:
THD (dB ) = 20 log
V
2
2
+
V
2
3
+V
2
4
+
V
2
5
+
V
2
6
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode at the
end of conversion. Track/Hold acquisition time is the
time required for the output of the track/hold amplifier
to reach its final value, within ±0.5 LSB, after the end
of conversion. See serial interface timing section for
more details.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distor-
tion) at the output of the A/D converter. The signal is
the rms amplitude of the fundamental. Noise is the sum
of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on
the number of quantization levels in the digitization
process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 16-bit converter, this is 98 dB.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7680 is tested using the CCIF standard where two
input frequencies nearthe top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
REV. PrE
–5–
5 Page 
AD7680
PRELIMINARY TECHNICAL DATA
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
www.DataSheet4U.com
6-lead SOT23 (RJ-6)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
0.059 (1.50)
6 5 4 0.118 (3.00)
0.098 (2.50)
123
PIN
1 0.037 (0.95)
BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.006 (0.15)
0.000 (0.00)
0.020 (0.50) SEATING
0.010 (0.25) PLANE
10 °
0.009 (0.23) 0 °
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
8-lead MSOP Package [MSOP]
(RM-8)
3.00
BSC
3.00
BSC
8
1
5
4
PIN 1
0.65 BSC
4.90
BSC
0.15
0.00
SEATING
PLANE
1.10 MAX
0.38
0.22
0.23
0.08
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-187AA
0.80
0.40
–11–
REV. PrE
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet AD7680.PDF ] | |
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