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GS8150V36AB-300 fiches techniques PDF

GSI Technology - 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM

Numéro de référence GS8150V36AB-300
Description 1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM
Fabricant GSI Technology 
Logo GSI Technology 





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GS8150V36AB-300 fiche technique
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GS8150V18/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250
119-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
18Mb Register-Register Late Write SRAM
250 MHz–357 MHz
1.8 V VDD
1.5 V or 1.8 V HSTL I/O
Features
• Register-Register Late Write mode, Pipelined Read mode
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• ZQ controlled programmable output drivers
• Dual Cycle Deselect
• Fully coherent read and write pipelines
• Byte write operation (9-bit bytes)
• Differential HSTL clock inputs, K and K
• Asynchronous output enable
• Sleep mode via ZZ
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• JEDEC-standard 119-bump BGA package
• Pb-Free 119-bump BGA package available
Family Overview
GS8150V18/36A are 18,874,368-bit (18Mb) high
performance SRAMs. This family of wide, very low voltage
HSTL I/O SRAMs is designed to operate at the speeds needed
to implement economical high performance cache systems.
Functional Description
Because GS8150V18/36A are synchronous devices, address
data inputs and read/write control inputs are captured on the
rising edge of the input clock. Write cycles are internally self-
timed and initiated by the rising edge of the clock input. This
feature eliminates complex off-chip write pulse generation
required by asynchronous SRAMs and simplifies input signal
timing.
GS8150V18/36A support pipelined reads utilizing a rising-
edge-triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
GS8150V18/36A are implemented with high performance
HSTL technology and are packaged in a 119-bump BGA.
Mode Control
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS8150V18/36A support single clock Pipeline mode,
which directly affects the two mode control select pins. In
order for the part to fuction correctly, and as specified, M1
must be tied to VSS and M2 must be tied to VDD or VDDQ.
This must be set at power-up and should not be changed during
operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Pipeline
Parameter Synopsis
Cycle
tKHQV
Curr (x18)
Curr (x36)
-357 -333 -300 -250 Unit
2.8 3.0 3.3 4.0 ns
1.4 1.5 1.6 2.0 ns
600 550 500 450 mA
650 600 550 500 mA
Rev: 1.04 4/2005
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

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