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PDF ADC12DL080 Data sheet ( Hoja de datos )
| Número de pieza | ADC12DL080 | |
| Descripción | Dual 12-Bit / 80 MSPS - A/D Converter for IF Sampling | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 2006
www.DataSheet4U.com
ADC12DL080
Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling
General Description
The ADC12DL080 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 80 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 600
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC12DL080 achieves 11.0 effective bits
at Nyquist and consumes just 447mW at 80 MSPS. The
Power Down feature reduces power consumption to 50 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. Duty cycle stabilization
and output data format are selectable. The output data can
be set for offset binary or two’s complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL080 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of −40˚C to +85˚C. An evaluation board is
available to ease the evaluation process.
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Internal or External reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n Duty Cycle Stabilizer
n Pin compatible with ADC12DL040, ADC12DL065,
ADC12DL066
Key Specifications
n Resolution
n Max Conversion Rate
n DNL
n SNR (fIN=40MHz)
n SNR (fIN=200MHz)
n SFDR (fIN=40MHz)
n SFDR (fIN=200MHz)
n Power Consumption
— Operating
— Power Down Mode
12 Bits
80 MSPS
±0.4 LSB (typ)
69 dB (typ)
67 dB (typ)
82 dB (typ)
81 dB (typ)
447 mW (typ)
50 mW (typ)
Applications
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL, Cable Modems
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS201694
20169401
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
www.DataSheet4U.com
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG POWER
Positive analog supply pins. These pins should be connected
9, 18, 19,
62, 63
VA
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
capacitors located near the power pins, and with a 10 µF
capacitor.
3, 8, 10, 17,
20, 61, 64
AGND
The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to the
33, 48
VD
same quiet +3.3V source as is VA and be bypassed to DGND
with a 0.1 µF capacitor located near the power pins, and with a
10 µF capacitor.
32, 49
DGND
The ground return for the digital supply.
Positive driver supply pin for the ADC12DL080’s output drivers.
This pin should be connected to a voltage source of +2.4V to
30, 51
VDR
VD and be bypassed to DRGND with a 0.1 µF capacitor. This
supply should also be bypassed with a 10 µF capacitor. VDR
should never exceed the voltage on VD. All 0.1 µF bypass
capacitors should be located near the supply pin.
The ground return for the digital supply for the ADC12DL080’s
23, 31, 40,
50, 58
DRGND
output drivers. These pins should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12DL080’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
5 www.national.com
5 Page 
Timing Diagram
www.DataSheet4U.com
Transfer Characteristic
Output Timing
20169409
FIGURE 1. Transfer Characteristic
11
20169410
www.national.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADC12DL080.PDF ] | |
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