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PDF TDA7333 Data sheet ( Hoja de datos )
| Número de pieza | TDA7333 | |
| Descripción | RDS/RBDS PROCESSOR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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TDA7333www.DataSheet4U.com
RDS/RBDS PROCESSOR
1 Features
■ 3rd ORDER HIGH RESOLUTION SIGMA
DELTA CONVERTER FOR MPX SAMPLING
■ DIGITAL DECIMATION AND FILTERING
STAGES
■ DEMODULATION OF EUROPEAN RADIO
DATA SYSTEM (RDS)
■ DEMODULATION OF USA RADIO
BROADCAST DATA SYSTEM (RBDS)
■ AUTOMATIC GROUP- AND BLOCK
SYNCHRONIZATION WITH FLYWHEEL
MECHANISM
■ ERROR DETECTION AND CORRECTION
■ PROGRAMMABLE INTERRUPT SOURCE
(RDS BLOCK,TA)
■ I2C/SPI BUS INTERFACE
■ COMMON QUARTZ FREQUENCY 8.55 MHz
or 8.664MHz
Figure 1. Package
TSSOP16
Table 1. Order Codes
Part Number
TDA7333
Package
TSSOP16
■ 3.3V POWER SUPPLY, 0.35 µm CMOS
TECHNOLOGY
2 Description
The TDA7333 is a RDS/RDBS signal processor,
intended for recovering the inaudible RDS/RBDS
informations which are transmitted on most FM ra-
dio broadcasting stations.
Figure 2. Block Diagram
Cref Cref Cref
REF1 REF2 REF3
432
Cxti Cxto
16pF
16pF
XTI
9
XTO
10
VDDA
1
VSS
5
VDDD
7
OSCILLATOR
MPX
Cmpx
16
SIGMA DELTA
converter
SINC4
filter
sinc4reg
BANDPASS
filter
INTERPOLATOR
MPX
SCL_CLK 11
SDA_DATAIN 12
SA_DATAOUT 13
CSN 14
January 2005
TEST LOGIC
&
PIN MUX's
tm resetn
68
TM RESETN
sdaout
sdain I2C/SPI
sck interface
spi
testreg
MPX
RDS
demodulator &
synchronisation
INTN
15 INTN
Rev. 1
1/21
1 page  
TDA7333
Table 6. Electrical Characteristics (continued)
Symbol
Parameter
Rp
fstop
Rs
Mi
I2C
fI2C
SPI
fSPI
tch
tcl
tcsu
tcsh
todv
toh
td
tsu
th
Passband Ripple
Stopband Corner Frequencies
Stopband Attenuation
Interpolation Factor
clock frequency in I2C mode
clock frequency in SPI mode
clock high time
clock low time
chip select setup time
chip select hold
output data valid
output hold
deselect time
data setup time
data hold time
Test Conditions
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Min.
-0.5
53.0
Values
Typ.
-43
32
Max.
+0.5
61
Unit
dB
kHz
dB
400 kHz
450
450
500
500
0
1000
200
200
1 MHz
ns
ns
ns
ns
250 ns
ns
ns
ns
ns
7 Functional Description
7.1 Overview
The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the
inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations.
Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing
is done in the digital domain and therefore very economical. After filtering the highly oversampled output
of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and
the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a group
and block wise information. This processing includes an error detection and error correction algorithm. In
addition, an automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS proces-
sor and the host.
The device operates in accordance with the EBU (European Broadcasting Union) specifications.
7.2 Sigma Delta Converter
The Sigma Delta Modulator is a 3rd order (second order-first order cascade) structure. Therefore a multibit out-
put (2 bit streams) represents the analog input signal. A next digital noise canceller will take the 2 bit streams
and calculates a combined stream which is then fed to the decimation filter. The modulator works at a sampling
frequency of XTI/2. The oversampling factor in relation to the band of interest (57 kHz +- 2.4 kHz) is 38.
7.3 Sinc4/16 Decimation Filter
The oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter.
This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta mod-
ulator.
5/21
5 Page 
TDA7333
7.7 Programming through Serial bus interface
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The serial bus interface is used to access the different registers of the chip. It is able to handle both I2C and SPI
transfer protocols, the selection between the two modes is done thanks to the pin CSN :
– if the pin CSN is high, the interface operates as an I2C bus.
– if the pin CSN is asserted low, the interface operates as a SPI bus.
In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.
Depending on the transfer mode, external pins have alternate functions as following:
Table 7.
pin
SCL_CLK
SDA_DATAIN
SA_DATAOUT
function in
SPI mode (CSN=0)
CLK (serial clock)
DATAIN (data input)
DATAOUT (data output)
function in
I2C mode (CSN=1)
SCL (serial clock)
SDA (data line)
SA (slave address)
Eight registers are available with read or read/write access rights as following :
Table 8.
register
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
rds_bd_ctrl[7:0]
sinc4reg[7:0]
testreg[7:0]
access rights
read/write
read
read
read
read
read/write
read/write
read/write
The meaning of each bit is described below :
function
interrupt source setting,synch., bne information
quality counter, actual block name
error correction status, buffer ovf information
high byte of current RDS block
low byte of current RDS block
frequency, quality sensitivity, plls setting
sinc4 filter settings (for internal use only)
test modes (for internal use only)
11/21
11 Page | ||
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| PDF Descargar | [ Datasheet TDA7333.PDF ] | |
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