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PDF TDA7333N Data sheet ( Hoja de datos )
| Número de pieza | TDA7333N | |
| Descripción | RDS/RBDS processor | |
| Fabricantes | STMicroelectronics | |
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TDA7333N
RDS/RBDS processor
Features
■ 3rd order high resolution sigma delta converter
for MPX sampling
■ Digital decimation and filtering stages
■ Demodulation of european radio data system
(RDS)
■ Demodulation of USA radio broadcast data
system (RBDS)
■ Automatic group and block synchronization
with flywheel mechanism
■ Error detection and correction
■ RAM buffer with a storage capacity of 24 RDS
blocks and related status information
■ Programmable interrupt source (RDS block A,
B, or D, TA, TA EON)
■ I2C/SPI bus interface
■ Input frequency range 4-21 MHz
■ Power down mode
■ 3.3 V power supply, 0.35 µm CMOS
technology
TSSOP16
Description
The TDA7333N circuit is a RDS/RDBS signal
processor, intended for recovering the inaudible
RDS/
RBDS informations which are transmitted on most
FM radio broadcasting stations..
Table 1. Device summary
Order code
Operating temp. range, °C
TDA7333N
TDA7333NTR
-40 to +85
-40 to +85
Package
TSSOP16
TSSOP16
Packing
Tube
Tape & reel
June 2008
Rev 3
1/36
www.st.com
1
1 page  
TDA7333N
List of figures
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Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Fractional PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Group and block synchronization diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Example for flywheel mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RAM buffer usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RAM buffer update depends on “syncw” bit rds_bd_ctrl[0] . . . . . . . . . . . . . . . . . . . . . . . . . 18
RAM buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
I2C write operation example: write of rds_int and rds_bd_ctrl registers . . . . . . . . . . . . . . . 28
I2C read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I2C read access example 1: read of 5 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C read access example 2: read of 1 byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write rds_int, rds_bd_ctrl and pll_reg4 registers in SPI mode,
reading RDS data and related flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers. . . . 31
Write rds_int registers in SPI mode, reading 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TSSOP16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5/36
5 Page 
TDA7333N
3 Functional description
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3.1 Overview
The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip.
It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio
broadcasting stations.
The oscillator frequency can be derived from the tuner with typical value of 10.25 MHz . The
device can operate with frequencies in the range of 4-21 MHz. Therefor the fractional PLL
must be initialized through I2C/SPI interface to generate the internal 8.55 MHz or 8.664 MHz
reference clock with a freq. tolerance of ±0.7 kHz.
Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all
further processing is done in the digital. After filtering the highly over sampled output of the
A/D converter, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal
and the quality information. A next RDS/RBDS decoder will synchronize the bit wise RDS
stream to a group and block wise information. This processing includes an error detection
and error correction algorithm. In addition, an automatic flywheel control avoids overheads
in the data exchange between the RDS/RBDS processor and the host.
The device operates in accordance with the CENELEC Radio Data System (RDS)
specification EN50067.
3.2 Fractional PLL
Figure 3. Fractional PLL
Input
Divider
Phase
Comperator
& VCO
f(vco)
Output
Divider
Fractional
Divider
Mux
PLL Controller
11/36
11 Page | ||
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| PDF Descargar | [ Datasheet TDA7333N.PDF ] | |
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