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PDF SC16C654B Data sheet ( Hoja de datos )
| Número de pieza | SC16C654B | |
| Descripción | 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.) | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C654B/654DB
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte
FIFOs and infrared (IrDA) encoder/decoder
Rev. 02 — 20 June 2005
Product data sheet
1. General description
The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter
(QUART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
It comes with an Intel or Motorola interface.
The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C654B/654DB. Some of these added features are
the 64-byte receive and transmit FIFOs, automatic hardware or software flow control and
infrared encoding/decoding. The selectable auto-flow control feature significantly reduces
software overload and increases system efficiency while in FIFO mode by automatically
controlling serial data flow using RTS output and CTS input signals. The
SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the
HVQFN48 package.) On-board status registers provide the user with error indications,
operational status, and modem interface control. System interrupts may be tailored to
meet user requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, HVQFN48 and LFBGA64 packages.
On the HVQFN48 package, only channel C has all the modem pins. Channel A and
channel B have only RTS and CTS pins, and channel D does not have any modem pin.
2. Features
s 4 channel UART
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range (−40 °C to +85 °C)
s SC16C654B is pin and software compatible with the industry-standard
ST16C454/554, ST16C654, ST68C454/554, TL16C554
s SC16C654DB is pin and software compatible with ST16C654D, and software
compatible with ST16C454/554, ST68C454/554, TL16C554
s Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V
s 5 V tolerant inputs
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Automatic software (Xon/Xoff)/hardware (RTS/CTS) flow control
s Programmable Xon/Xoff characters
1 page  
Philips Semiconductors
SC16C654B/654DBwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
5. Pinning information
5.1 Pinning
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
SC16C654BIA68
16 mode
Fig 3. Pin configuration for PLCC68 (16 mode)
60 DSRD
59 CTSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
002aaa873
9397 750 14965
Product data sheet
Rev. 02 — 20 June 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 58
5 Page 
Philips Semiconductors
SC16C654B/654DBwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 2:
Symbol
CSA
CSB
CSC
CSD
Pin description …continued
Pin
PLCC68 LQFP64 HVQFN48 LFBGA6
4
16 7
5
E1
20 11 9
G1
50 38 31
G9
54 42 35
E9
CTSA 11
2
1
CTSB 25 16 12
CTSC 45 33 26
CTSD 59 47 -
C1
J2
K10
B10
D0 to D2, 66 to 68 53 to 55, 39 to 41,
D3 to D7 , 1 to 5 56 to 60 42 to 46
DSRA 10
1
-
DSRB 26 17 -
DSRC 44 32 25
DSRD 60 48 -
DTRA 12
3
-
DTRB 24 15 -
DTRC 46 34 27
DTRD 58 46 -
B7, A7,
B6, A6,
B5, A5,
B4, A4
B1
K1
K9
B9
D1
J1
J10
C9
GND
INTA
INTB
INTC
INTD
6, 23,
40, 57
15
21
49
55
14, 28,
45, 61
6
12
37
43
21, 37, 47 B3, K7,
H1, D9
4 D2
10 G2
30 G10
36 D10
Type Description
I Chip Select A, B, C, D (active LOW). This function is
associated with the 16 mode only, and for individual
channels ‘A’ through ‘D’. When in 16 mode, these pins
enable data transfers between the user CPU and the
SC16C654B/654DB for the channel(s) addressed. Individual
UART sections (A, B, C, D) are addressed by providing a
logic 0 on the respective CSA to CSD pin. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.
I Clear to Send (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on the
CTS pin indicates the modem or data set is ready to accept
transmit data from the SC16C654B/654DB. Status can be
tested by reading MSR[4]. This pin only affects the transmit
or receive operations when Auto CTS function is enabled via
the Enhanced Feature Register EFR[7] for hardware flow
control operation.
I/O Data bus (bi-directional). These pins are the 8-bit, 3-state
data bus for transferring information to or from the controlling
CPU. D0 is the least significant bit and the first data bit in a
transmit or receive serial data stream.
I Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem or data set is powered-on and is
ready for data exchange with the UART. This pin has no
effect on the UART’s transmit or receive operation.
O Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through D. A
logic 0 on this pin indicates that the SC16C654B/654DB is
powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set
the DTR output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
This pin has no effect on the UART’s transmit or receive
operation.
I Signal and power ground.
O Interrupt A, B, C, D (active HIGH). This function is
associated with the 16 mode only. These pins provide
individual channel interrupts INTA to INTD. INTA to INTD are
enabled when MCR[3] is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty, or when a modem status flag is detected. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.
9397 750 14965
Product data sheet
Rev. 02 — 20 June 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 58
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SC16C654B.PDF ] | |
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