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PDF BH62UV4000 Data sheet ( Hoja de datos )
| Número de pieza | BH62UV4000 | |
| Descripción | Ultra Low Power/High Speed CMOS SRAM 512K X 8 bit | |
| Fabricantes | Brilliance Semiconductor | |
| Logotipo |  |
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Ultra Low Power/High Speed CMOS SRAM
512K X 8 bit
Green package materials are compliant to RoHS
BH62UV4000www.DataSheet4U.com
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.6V Operation current : 10mA (Max.)at 55ns
2mA (Max.)at 1MHz
Standby current : 2.0uA (Typ.) at 3.0V/25OC
VCC = 1.2V Data retention current : 1.0uA at 25OC
Ÿ High speed access time :
-55 55ns (Max.) at VCC=1.65~3.6V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n POWER CONSUMPTION
n DESCRIPTION
The BH62UV4000 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 524,288 by 8 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25OC and maximum access time of 55ns at
1.65V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BH62UV4000 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH62UV4000 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 400mil TSOP-II, 600mil Plastic DIP,
8mmx13.4mm STSOP, 8mmx20mm TSOP and 36-ball BGA
package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Icc STANDBY
(ICCSB1, Max)
VCC=3.6V VCC=1.8V
BH62UV4000DI
BH62UV4000EI
BH62UV4000HI
BH62UV4000PI
BH62UV4000SI
BH62UV4000STI
BH62UV4000TI
Industrial
-40OC to +85OC
10uA
10uA
POWER DISSIPATION
VCC=3.6V
Icc Operating
(ICC, Max)
1MHz 10MHz
fMax.
1MHz
VCC=1.8V
10MHz
2mA 6mA 10mA 1.5mA 5mA
fMax.
8mA
PKG TYPE
DICE
TSOP-II
BGA-36-0608
PDIP-32
SOP-32
STSOP-32
TSOP-32
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BH62UV4000STI
BH62UV4000TI
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
A13
A12
A11
A10
Address
10
1024
A9 Input
A8
Row
A7 Buffer
Decoder
A6
A5
A4
Memory Array
1024 x 4096
4096
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1•
2
3
4
5
6
7 BH62UV4000EI
8 BH62UV4000PI
9 BH62UV4000SI
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
123456
A A0 A1 NC A3 A6 A8
B DQ4 A2 WE A4 A7 DQ0
C DQ5
NC A5
DQ1
D VSS
VCC
E VCC
VSS
F DQ6
A18 A17
DQ2
G DQ7 OE CE A16 A15 DQ3
H A9 A10 A11 A12 A13 A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
VCC
GND
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
8
8
Column I/O
Write Driver
Sense Amp
512
Column Decoder
9
Address Input Buffer
A18 A16 A15 A14 A0 A17 A3 A2 A1
36-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV4000
1
Revision 1.2
Aug.
2006
1 page  
READ CYCLE 2 (1,3,4)
CE
DOUT
READ CYCLE 3 (1, 4)
ADDRESS
OE
CE
DOUT
tACS
tCLZ(5)
tRC
tAA
tOE
tOLZ
tACS
tCLZ(5)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
BH62UV4000www.DataSheet4U.com
tCHZ (5)
tOH
tOHZ(5)
tCHZ(1,5)
R0201-BH62UV4000
5
Revision 1.2
Aug.
2006
5 Page 
n PACKAGE DIMENSIONS (continued)
32 17
1
ZD
e
YY
b 16
D
Y
-T-
SEATING PLANE
BH62UV4000www.DataSheet4U.com
DIMENSION
(MM)
DIMENSION
(INCH)
MIN. NOM. MAX. MIN. NOM. MAX.
A 1.20 0.047
A1 0.05
0.10
0.15
0.002 0.004 0.006
A2 0.95
1.00
1.05
0.037 0.039 0.042
b 0.30
0.52 0.012
0.020
b1 0.30
c 0.12
0.40 0.45
0.21
0.012
0.005
0.016
0.018
0.008
c1 0.10
0.127 0.16
0.004 0.005 0.006
D 20.82 20.95 21.08 0.820 0.825 0.830
E 11.56 11.76 11.96 0.455 0.463 0.471
"X" E1 10.03 10.16 10.29 0.394 0.400 0.405
e 1.27 BASIC
0.050 BASIC
L 0.40 0.50 0.60 0.016 0.020 0.024
L1 0.25 BASIC
0.010 BASIC
L2 0.8 REF
0.031 REF
R 0.12
0.25 0.005
0.010
R1 0.12
0.005
ZD 0.95 REF
0.037 REF
Y 0.10 0.004
RAD R
L RAD R1
L2
GAGE PLANE
b
b1
WITH PLATING
BASE METAL
DETAIL "X"
SECTION Y-Y
TSOP II - 32
NOTE:
1. CONTROLLING DIMENSION : MILLIMETERS.
2. REFREENCE DOCUMENT : JEDEC MS-024
3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
R0201-BH62UV4000
11
Revision 1.2
Aug.
2006
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet BH62UV4000.PDF ] | |
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