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PDF LC8213K Data sheet ( Hoja de datos )

Número de pieza LC8213K
Descripción Image Data Compression/Expansion Processor
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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Ordering number : EN *5753
CMOS LSI
LC8213K
Image Data Compression/Expansion Processor
Preliminary
Overview
The LC8213K compresses and expands the binary image
data used in fax and similar applications and can be used
in office automation equipment such as G3 or G4
facsimile systems, image filing systems, digital copiers,
and engineering workstations. The LC8213K supports
encoding methods that conform to the MH (Modified
Huffman), MR (Modified relative element address
designate), and MMR (Modified MR) encoding
techniques as stipulated in the ITU-T T.4 and T.6
recommendations.
Features
• Conforms to the ITU-T T.4 and T.6 MH, MR, and
MMR encoding methods.
• Supports G3 and G4 facsimile.
• Handles up to 64k bits in the main scan direction.
• Line skip mode
• 8/16-bit image memory bus, 8-bit CPU bus
• Supports data transfers between the CPU bus and the
image memory bus.
• DMA transfer function for data transfers between image
memory and I/O devices
• Executes encoding processing and DMA transfers
simultaneously
• System clock frequency: Up to 25 MHz
• CMOS structure supporting low power dissipation
Package Dimensions
unit: mm
3174-QFP80E
[LC8213K]
SANYO: QIP80E
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input and output voltages
Allowable power dissipation
Operating temperature
Storage temperature
Soldering conditions
Symbol
VDD max
VI, VO
Pd max
Topr
Tstg
Condition
Ta 70°C
Hand soldering: 3 seconds
Reflow soldering: 10 seconds
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
500
–30 to +70
–55 to +125
350
235
Unit
V
V
mW
°C
°C
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93097HA (OT) No. 5753-1/5

1 page




LC8213K pdf
LC8213K
• CPU interface
The LC8213K has an 8-bit data bus. Various aspects of the operating mode can be set by accessing the interface
registers. Since the LC8213K provides interface pins for a DMA controller, DMA transfers with memory on the CPU
bus are supported.
• Image memory interface
The image memory has a 16-MB address space. A data bus width of either 8 or 16 bits can be selected.
• DMA transfer function
This function performs DMA transfers between image memory and I/O devices using the on-chip DMA controller. The
number of lines of data transferred can be set to any value up to 64k lines.
• Data transfers
Data can be transferred between the CPU bus and the image memory bus without encoding or decoding.
• Pad bit processing
Applications can select whether or not to perform pad bit processing. Pad bit processing consists of adding bits set to 0 at
the end of each line of encoded data so that the data for that line is an even multiple of 8 bits.
• Parameter settings
The LC8213K supports the following parameters, which can be set to any value in the indicated range.
• Number of bits processed on a single line (in byte units): 1 to 8k bytes
• Source document width (in byte units):
1 to 8k bytes
• Number of lines processed:
1 to 64k lines
• Minimum number of bits transmitted per line:
0 to 64k bits
• K parameter for MR encoding:
0 to 64k
• Number of lines handled in DMA transfers:
1 to 64k lines
• Number of EOL codes that form the RTC code:
0 to 255
Since the source document width and the number of bits processed on a single line can be set separately, the LC8213K
supports encoding or decoding the data for a subsection of the source document.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
ΠAccept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1997. Specifications and information herein are subject to
change without notice.
No. 5753-5/5

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