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PDF UPD160300 Data sheet ( Hoja de datos )
| Número de pieza | UPD160300 | |
| Descripción | 192-BIT AC-PDP DRIVER | |
| Fabricantes | NEC Electronics | |
| Logotipo |  |
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PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD160300www.DataSheet4U.com
192-BIT AC-PDP DRIVER
DESCRIPTION
The µ PD160300 is a high-withstanding-voltage CMOS driver designed for use with a flat display panel such as a
PDP, VFD, or EL panel. It consists of a 192-bit bi-directional shift register, 192-bit latch and high-withstanding-voltage
CMOS driver. The logic block operates with a 5.0 V power supply and 3.3 V interface so that it can be directly
connected to a gate array and microcomputer (CMOS Level Input). The driver block provides a high-withstanding-
voltage output: 80 V.
The logic and driver blocks are made of CMOS circuits, consuming lower power.
FEATURES
• 3-ch, 6-ch and 6-ch (3-ch + 3-ch) input port switching is possible using the IBS1 and IBS2 pins
• Many outputs: 192-bit output
• Clock transfer is switchable via the SDS pin between single edge and double edge
• Data control with transfer clock (external) and latch
• High-speed data transfer: fCLK = 60 MHz MAX. (at loading of data)
• High withstanding voltage and high drive output: 80 V MAX., +13/–24 mA MAX.
• 3.3 V input interface (VDD1 = 5.0 V)
• High-withstanding-voltage CMOS structure
ORDERING INFORMATION
Part Number
µ PD160300N-xxx
Package
TCP (TAB package)
Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales
representatives.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are availabe in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16976EJ2V0PM00 (2nd edition)
Date Published June 2004 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
2003
1 page  
2. PIN CONFIGURATION (IC pad surface)
µPD160300N-xxx: TCP (TAB package)
VSS2
VDD2
VSS2
A6
A5
A4
A3
A2
A1
SDS
/LE
/CLR
CLK
/LBLK
/HBLK
VDD1
HZ
IBS1
IBS2
VSS1
R,/L
VSS2
VDD2
VSS2
IC pad
surface
Remark This figure does not specify the TCP package.
µ PD160300
www.DataSheet4U.com
O192
O191
O190
O189
O4
O3
O2
O1
Preliminary Product Information S16976EJ2V0PM
5
5 Page 
µ PD160300
(3) IBS1 = H, IBS2 = L: 6-bit input, SDS = L: single edge
www.DataSheet4U.com
CLK
/CLR
A1 (A6)
A2 (A5)
A3 (A4)
A4 (A3)
A5 (A2)
A6 (A1)
S1 (S192)
S2 (S191)
S3 (S190)
S4 (S189)
S5 (S188)
S6 (S187)
/LE
/LBLK
/HBLK
HZ
O1 (O192)
O2 (O191)
O3 (O190)
O4 (O189)
O5 (O188)
O6 (O187)
(Latch at the falling edge)
High-impedance
Remark Values in parentheses are when R,/L = L.
Preliminary Product Information S16976EJ2V0PM
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet UPD160300.PDF ] | |
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