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PDF M36W0R6050B1 Data sheet ( Hoja de datos )
| Número de pieza | M36W0R6050B1 | |
| Descripción | 64 Mbit Flash Memory and 32 Mbit PSRAM Multi-Chip Package | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M36W0R6050T1
M36W0R6050B1
64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory
and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package
Features
■ Multi-Chip Package
– 1 die of 64 Mbit (4 Mb × 16) Flash memory
– 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM
■ Supply voltage
– VDDF = VDDP = VDDQF = 1.7 V to 1.95 V
■ Low power consumption
■ Electronic signature
– Manufacturer Code: 20h
– Device code (top flash configuration),
M36W0R6050T1: 8810h
– Device code (bottom flash configuration),
M36W0R6050B1: 8811h
■ Package
– ECOPACK®
Flash memory
■ Programming time
– 8 µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■ Memory blocks
– Multiple Bank memory array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 66 MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70 ns
■ Dual operations
– Program Erase in one Bank while Read in
others
– No delay between Read and Write
operations
FBGA
Stacked TFBGA88
(ZA)
■ Block locking
– All blocks locked at Power-up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
■ Security
– 128-bit user programmable OTP cells
– 64-bit unique device number
■ Common Flash Interface (CFI)
■ 100 000 program/erase cycles per block
PSRAM
■ Access time: 70 ns
■ Asynchronous Page Read
– Page size: 8 words
– First access within page: 70 ns
– Subsequent read within page: 20 ns
■ Three Power-down modes
– Deep Power-Down
– Partial Array Refresh of 4 Mbits
– Partial Array Refresh of 8 Mbits
January 2007
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www.st.com
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1 page  
M36W0R6050T1, M36W0R6050B1
List of figures
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Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package outline. . 18
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5 Page 
M36W0R6050T1, M36W0R6050B1
Siwgnwawl.DdaetsacShriepetti4oUn.csom
2.12
PSRAM Chip Enable (E2P)
When de-asserted (Low), the Chip Enable input E2P, puts the device in Power-Down mode.
This is the lowest power mode according to the Configuration Register settings (see
M69KB048BD datasheet).
2.13
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.14
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory’s Command
Interface.
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is
the main power supplies for all Flash memory operations (Read, Program and Erase).
2.18
VDDP supply voltage
The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for
driving the refresh logic, even when the device is not being accessed.
2.19
VDDQF supply voltage
VDDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to
be powered independently of the Flash memory core power supply, VDDF.
11/22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M36W0R6050B1.PDF ] | |
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