|
|
Número de pieza | R4S76190 | |
Descripción | 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | |
Fabricantes | Renesas Technology | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de R4S76190 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
No Preview Available ! REJ09B0237-0500
The revision list can be viewed directly bywww.DataSheet4U.com
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7619 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family / SH7619 Series
SH7619 R4S76190
Rev.5.00
Revision Date: Mar. 15, 2007
1 page Configuration of This Manual
www.DataSheet4U.com
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 5.00 Mar. 15, 2007 Page v of xxxviii
5 Page Section 6 Interrupt Controller (INTC) ...................................................................83
6.1 Features...................................................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 83
6.2 Input/Output Pins................................................................................................................ 85
6.3 Register Descriptions.......................................................................................................... 85
6.3.1 Interrupt Control Register 0 (ICR0).................................................................... 86
6.3.2 IRQ Control Register (IRQCR) .......................................................................... 87
6.3.3 IRQ Status register (IRQSR) .............................................................................. 90
6.3.4 Interrupt Priority Registers A to G (IPRA to IPRG)........................................... 95
6.4 Interrupt Sources................................................................................................................. 97
6.4.1 External Interrupts .............................................................................................. 97
6.4.2 On-Chip Peripheral Module Interrupts ............................................................... 99
6.4.3 User Break Interrupt ........................................................................................... 99
6.4.4 H-UDI Interrupt .................................................................................................. 99
6.5 Interrupt Exception Handling Vector Table...................................................................... 100
6.6 Interrupt Operation ........................................................................................................... 102
6.6.1 Interrupt Sequence ............................................................................................ 102
6.6.2 Stack after Interrupt Exception Handling ......................................................... 104
6.7 Interrupt Response Time................................................................................................... 104
Section 7 Bus State Controller (BSC)..................................................................107
7.1 Features............................................................................................................................. 107
7.2 Input/Output Pins.............................................................................................................. 110
7.3 Area Overview.................................................................................................................. 111
7.3.1 Area Division.................................................................................................... 111
7.3.2 Shadow Area..................................................................................................... 112
7.3.3 Address Map ..................................................................................................... 112
7.3.4 Area 0 Memory Type and Memory Bus Width ................................................ 114
7.3.5 Data Alignment................................................................................................. 114
7.4 Register Descriptions........................................................................................................ 115
7.4.1 Common Control Register (CMNCR) .............................................................. 116
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B) ............... 117
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B) ................ 122
7.4.4 SDRAM Control Register (SDCR)................................................................... 138
7.4.5 Refresh Timer Control/Status Register (RTCSR)............................................. 139
7.4.6 Refresh Timer Counter (RTCNT)..................................................................... 141
7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 142
7.5 Operation .......................................................................................................................... 143
7.5.1 Endian/Access Size and Data Alignment.......................................................... 143
7.5.2 Normal Space Interface..................................................................................... 149
7.5.3 Access Wait Control ......................................................................................... 154
Rev. 5.00 Mar. 15, 2007 Page xi of xxxviii
11 Page |
Páginas | Total 70 Páginas | |
PDF Descargar | [ Datasheet R4S76190.PDF ] |
Número de pieza | Descripción | Fabricantes |
R4S76190 | 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | Renesas Technology |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |