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PDF ICS858020 Data sheet ( Hoja de datos )
| Número de pieza | ICS858020 | |
| Descripción | LOW SKEW 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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ICS858020www.DataSheet4U.com
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-CML FANOUT BUFFER
GENERAL DESCRIPTION
The ICS858020 is a high speed 1-to-4 Differential-
ICS to-CML Fanout Buffer and is a member of the
HiPerClockS™ HiPerClockS™family of high performance clock
solutions from ICS. The ICS858020 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow
other differential signal families such as LVDS, LVHSTL and
CML to be easily interfaced to the input with minimal use of
external components. The ICS858020 is packaged in a small
3mm x 3mm 16-pin VFQFN package which makes it ideal for
use in space-constrained applications.
FEATURES
• Four differential CML outputs
• One LVPECL differential clock input
• IN, nIN pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 3.2GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 225ps (maximum)
• Additive phase jitter, RMS: <0.03ps (typical)
• Propagation delay: 600ps (maximum)
• Operating voltage supply range:
VCC = 2.375V to 3.63V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
IN
VT
nIN
V
REF_AC
858020AK
PIN ASSIGNMENT
Q0
nQ0
16 15 14 13
IN 1
12 Q1
VT 2
11 nQ1
VREF_AC 3
10 Q2
nIN 4
9 nQ2
5678
Q1
nQ1
ICS858020
Q2 16-Lead VFQFN
nQ2 3mm x 3mm x 0.95 package body
K Package
Top View
Q3
nQ3
1 REV. A DECEMBER 10, 2007
1 page  
ICS858020www.DataSheet4U.com
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-CML FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Additive Phase Jitter at
155.52MHz = <0.03ps (typical)
10k 100k 1M 10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
858020AK
5 REV. A DECEMBER 10, 2007
5 Page 
ICS858020www.DataSheet4U.com
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-CML FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 4. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS858020 is: 28
Pin compatible with SY58020U
858020AK
11 REV. A DECEMBER 10, 2007
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS858020.PDF ] | |
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