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PDF ICS858012 Data sheet ( Hoja de datos )
| Número de pieza | ICS858012 | |
| Descripción | LOW SKEW 1-TO-2 DIFFERENTIAL-TO-2.5V 3.3V LVPECL FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS858012www.DataSheet4U.com
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS858012 is a high speed 1-to-2 Differential-
ICS to-2.5V, 3.3V LVPECL Fanout Buffer and is a
HiPerClockS™ member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS858012 is optimized for high speed and very
low output skew, making it suitable for use in demanding
applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated
differential input and VREF_AC pin allow other differential signal
families such as LVPECL, LVDS, LVHSTL and HCSL to be
easily interfaced to the input with minimal use of external
components. The ICS858012 is packaged in a small 3mm x
3mm 16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
FEATURES
• Two differential LVPECL outputs
• One differential LVPECL clock input
• IN, nIN pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency: 2GHz (typical)
• Output skew: <15ps (typical)
• Part-to-part skew: TBD
• Additive phase jitter, RMS: TBD
• Propagation delay: 350ps (typical)
• Operating voltage supply range:
VCC = 2.375V to 3.63V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Availabe in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
IN
VT
nIN
V
REF_AC
PIN ASSIGNMENT
Q0
nQ0
16 15 14 13
IN 1
12 Q0
VT 2
11 nQ0
VREF_AC 3
10 nQ1
nIN 4
9 Q1
5678
Q1
nQ1
ICS858012
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
858012AK
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS858012www.DataSheet4U.com
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
LVPECL
VEE
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
V
CC
nIN
V
IN
IN
VEE
Cross Points
V
IL
DIFFERENTIAL INPUT LEVEL
V
IH
nQx
PART 1
Qx
nQy
PART 2
Qy
t sk(pp)
nQx
Qx
nQy
Qy
t sk(o)
PART-TO-PART SKEW
nIN
IN
nQ0, nQ1
Q0, Q1
tPD
PROPAGATION DELAY
OUTPUT SKEW
VIN
VIN, VOUT
800mV
(typical)
VDIF_IN
VDIFF_IN, VDIFF_OUT
1.6V
(typical)
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
Clock 20%
Outputs
80%
tR
OUTPUT RISE/FALL TIME
858012AK
80%
tF
VSW I N G
20%
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 28, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS858012www.DataSheet4U.com
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-
2.5V, 3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS858012.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS858012 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 30mA = 108.9mW
• Power (outputs) = 30.2mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.63V, with all outputs switching) = 108.9mW + 60.4mW = 169.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.169W * 51.5°C/W = 93.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 4. THERMAL RESISTANCE θJA FOR 16 LEAD VFQFN, FORCED CONVECTION
θJA at 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
51.5°C/W
858012AK
www.icst.com/products/hiperclocks.html
11
REV. A NOVEMBER 28, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS858012.PDF ] | |
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