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KK74ACT109 fiches techniques PDF

KODENSHI KOREA - Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

Numéro de référence KK74ACT109
Description Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
Fabricant KODENSHI KOREA 
Logo KODENSHI KOREA 





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KK74ACT109 fiche technique
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
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KK74ACT109
The KK74ACT109 is identical in pinout to the LS/ALS109,
HC/HCT109. The KK74ACT109 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT109N Plastic
KK74ACT109D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X
X X H*
H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
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