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PDF HYB39S16160CT-10 Data sheet ( Hoja de datos )
| Número de pieza | HYB39S16160CT-10 | |
| Descripción | 16 MBit Synchronous DRAM | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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16 MBit Synchronous DRAM
HYB 39S16400/800/160CT-8/-10
• High Performance:
fCK(MAX.)
tCK3
tAC3
tCK2
tAC2
-8 -10 Units
125 100 MHz
8 10 ns
6 7 ns
10 12 ns
6 8 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Dual Banks controlled by A11 ( Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence:
Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• Full page (optional) for sequencial wrap
around
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control
• Dual Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPI-44 400mil width (× 4, × 8)
P-TSOPII-50 400mil width (× 16 )
• -8 version for PC100 applications
The HYB39S16400/800/160CT are dual bank Synchronous DRAM’s based on SIEMENS 0.25 µm
process and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kbit
× 16 respectively. These synchronous devices achieve high speed data transfer rates up to 125
MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output
data to a system clock. The chip is fabricated with SIEMENS’ advanced 16 MBit DRAM process
technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up
to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V ± 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
1998-10-01
1 page  
HYB 39S16400/800/160CT-8/-10
16 MBit Synchwrwown.DoautasSheDetR4UA.coMm
Signal Pin Description (cont’d)
Pin
VDD
VSS
VDDQ
VSSQ
Type Signal Polarity Function
Supply –
–
Power and ground for the input buffers and the core logic.
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
CKE CKE Buffer
CLK CLK Buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
12
12
CS CS Buffer
RAS RAS Buffer
CAS CAS Buffer
WE WE Buffer
Self
Refresh Clock
Row Decoder
Row
Address
Counter
Bank A
Row/Column
Select
11
Predecode A
3 Sequential
Control
Bank A
11
Mode Register
3 Sequential
Control
Bank B
11
Predecode B
Bank B
Row/Column
Select
2048 x 1024
Memory Bank A
2048
1024
Sense Amplifiers
Column Decoder
and DQ Gate
8
Data Latches
8
8
Data Latches
8
Column Decoder
and DQ Gate
Sense Amplifiers
1024
DQM DQM Buffer
Row Decoder
Memory Bank B
2048 x 1024
2048
Block Diagram for HYB 39S16400CT (2 banks × 2 M × 4 SDRAM)
4
DQ0
DQ1
DQ2
DQ3
SPB02835
Semiconductor Group
5
1998-10-01
5 Page 
HYB 39S16400/800/160CT-8/-10
16 MBit Synchwrwown.DoautasSheDetR4UA.coMm
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock before the
last data out for CAS latency 2 amd two clocks for CAS latency 3. If CAS10 is high when a Write
Command is issued, the Write with Auto Precharge function is initiated. The SDRAM
automatically enters the precharge operation one clock delay form the last data-in for CAS latencies
of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as tDPL .
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time tWR from the last burst data to apply the precharge command.
Bank Selection by Address Bits
Bank A only
Bank B only
Both A and B
A10
Low
Low
High
A11
Low
High
Don’t Care
Semiconductor Group
11
1998-10-01
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HYB39S16160CT-10.PDF ] | |
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