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PDF HYB39S16160CT-6 Data sheet ( Hoja de datos )
| Número de pieza | HYB39S16160CT-6 | |
| Descripción | 1M x 16 MBit Synchronous DRAM | |
| Fabricantes | Siemens Semiconductor | |
| Logotipo |  |
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1M x 16 MBit Synchronous DRAM
for High Speed Graphics Applications
www.DataSheet4U.com
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
• High Performance:
-6 -7 Units
fCKmax @ CL=3 166 143 MHz
tCK3
6 7 ns
tAC3
5 5.5 ns
fCKmax @ CL=2 125 115 MHz
tCK2
8 9 ns
tAC2
6 6 ns
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Dual Banks controlled by A11 ( Bank Select)
• Programmable CAS Latency : 2, 3
• Programmable Wrap Sequence : Sequential
or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• full page(optional) for sequencial wrap
around
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read / Write control
• Dual Data Mask for byte control ( x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles / 64 ms
• Latency 2 @ 125 MHz
• Latency 3 @ 166 MHz
• Random Column Address every CLK
( 1-N Rule)
• Single 3.3V +/- 0.3V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPII-50 400mil width ( x16 )
The HYB39S16160CT-6/-7 are high speed dual bank Synchronous DRAM’s based on SIEMENS
0.25µm process and organized as 2 banks x 512kbit x 16. These synchronous devices achieve high
speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’
advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
10.98
1 page  
www.DataSheet4U.com
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Operation
Standby, Ignore RAS, CAS, WE and Address
Row Address Strobe and Activating a Bank
Column Address Strobe and Read Command
Column Address Strobe and Write Command
Precharge Command
Burst Stop Command
Self Refresh Entry
Mode Register Set Command
Write Enable/Output Enable
Write Inhibit/Output Disable
No Operation (NOP)
CS RAS CAS WE (L/U)DQM
HXXX
X
L LHH
X
LHLH
X
LHL L
X
L LHL
X
L HH L
X
L L LH
X
LLLL
X
XXXX
L
XXXX
H
L HHH
X
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be
programmed in the SDRAM mode register. The mode set operation must be done before any
activate command after the initial power up. Any content of the mode register can be altered by re-
executing the mode set command. Both banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the following table.
Semiconductor Group
5
5 Page 
www.DataSheet4U.com
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, VCC = 3.3V ± 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Operating Current
Precharge
Standby Current
in Power Down
Mode
Precharge
Standby Current
in Non-power
down Mode
Active Standby
Current in Power
Down Mode
Active Standby
Current in Non-
power Down
Mode
Burst Operating
Current
Auto (CBR)
Refresh Current
Self Refresh
Symbol
Test Condition
CAS -6 -7
Latency max. max.
Note
Icc1
Burst Length = 4
trc>=trc (min.)
tck>=tck(min.), Io = 0mA
2 bank interleave operation
150 130 mA 1, 2
Icc2P CKE<=VIL(max),
tck>=tck(min.)
2 2 mA
Icc2PS CKE<=VIL(max),
tCK=infinite
1 1 mA
Icc2N CKE>=VIH(min),
tck>=tck(min.) input signals
changed once in 3 cycles
Icc2NS CKE>=VIH(min),
tCK=infinite, input signals
are stable
Icc3P CKE<=VIL(max),
tck>=tck(min.)
Icc3PS CKE<=VIL(max),
tCK=infinite, inpit signals
are stable
Icc3N CKE>=VIH(min),
tck>=tck(min.),
changed once in 3 cycles
Icc3NS CKE>=VIH(min),
tCK=infinite, input signals
are stable
Icc4
Burst Length = full page
trc = infinite
tck >= tck (min.), IO = 0 mA
2 banks activated
Icc5 trc>=trc(min)
Icc6 CKE=<0,2V
15 15 mA CS=
High
5 5 mA
3 3 mA
2 2 mA
25 25 mA CS=
High,
1
15 15 mA
100 85 mA 1, 2
60 50 mA 1, 2
mA
1 1 mA 1, 2
Notes:
1. The specified values are valid when addresses are changed no more than three times during trc(min.) and
when No Operation commands are registered on every rising clock edge during tRC(min).
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
Semiconductor Group
11
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| PDF Descargar | [ Datasheet HYB39S16160CT-6.PDF ] | |
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