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PDF HYB39S16400AT-8 Data sheet ( Hoja de datos )
| Número de pieza | HYB39S16400AT-8 | |
| Descripción | 16 MBit Synchronous DRAM | |
| Fabricantes | Siemens Semiconductor | |
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16 MBit Synchronous DRAM
(second generation)
HYB 39S16400/800/160AT-8/-10
Advanced Information
• High Performance:
CAS latency = 3
fCK
tCK3
tAC3
-8
125
8
7
-10 Units
100 MHz
10 ns
8 ns
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1, 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (× 4, × 8)
• Dual Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-44-1 400 mil width (× 4, × 8)
P-TSOPII-50-1 400 mil width (× 16)
The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”
and “C” and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kBit × 16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V ± 0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
1 page  
HYB 39S16400/800/160AT-8/-10
16 MBit Synchwrwown.DoautasSheDetR4UA.coMm
Signal Pin Description (cont’d)
Pin Type Signal Polarity Function
DQM
LDQM
UDQM
Input
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
VDD
VSS
VDDQ
VSSQ
Supply –
Supply –
–
–
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Semiconductor Group
5
1998-10-01
5 Page 
HYB 39S16400/800/160AT-8/-10
16 MBit Synchwrwown.DoautasSheDetR4UA.coMm
Read and Write Access Mode
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and
CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define
either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8,
full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the refresh
interval time limits the number of random column accesses. A new burst access can be done even
before the previous burst ends. The interrupt operation at every clock cycles is supported. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the
full burst length. An interrupt which accompanies with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.
When two banks are activated sequentially, interleaved bank read or write operations are possible.
With the programmed burst length, alternate access and precharge operations on two banks can
realize fast serial data access modes among many different pages. Once two banks are activated,
column to column interleave operation can be done between two different pages.
Refresh Mode
SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All
of banks must be precharged before applying any refresh mode. An on-chip address counter
increments the word and the bank addresses and no bank information is required for both refresh
modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and
WE are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one tRC delay is required prior to any access command.
Semiconductor Group
11
1998-10-01
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet HYB39S16400AT-8.PDF ] | |
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