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PDF HYB39S128400FT Data sheet ( Hoja de datos )
| Número de pieza | HYB39S128400FT | |
| Descripción | 128-MBit Synchronous DRAM | |
| Fabricantes | Qimonda | |
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October 2007
www.DataSheet4U.com
HYB39S128400F[E/T](L)
HY[B/I]39S128800F[E/T](L)
HY[B/I]39S128160F[E/T](L)
HYB39S128407FE
128-MBit Synchronous DRAM
Green Product
SDRAM
Data Sheet
Rev. 1.32
1 page  
Data Sheet
www.DataSheet4U.com
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
2 Chip Configuration
This chapter contains the pin configuration table, the TSOP package drawing, and the block diagrams for the ×4, ×8, ×16
organization of the SDRAM.
2.1 Pin Description
Listed below are the pin configurations sections for the various signals of the SDRAM
TABLE 4
Pin Configuration of the SDRAM
Ball No. Name Pin Buffer
Type Type
Function
Clock Signals ×4/×8/×16 Organization
38
CLK I
LVTTL Clock Signal CK
37
CKE I
LVTTL Clock Enable
Control Signals ×4/×8/×16 Organization
18
RAS I
LVTTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
17
CAS I
LVTTL
16
WE I
LVTTL
19
CS I
LVTTL Chip Select
Address Signals ×4/×8/×16 Organization
20
BA0 I
LVTTL Bank Address Signals 1:0
21
BA1 I
LVTTL
23
A0 I
LVTTL Address Signal, Address Signal 10/Auto precharge
24
A1 I
LVTTL
25
A2 I
LVTTL
26
A3 I
LVTTL
29
A4 I
LVTTL
30
A5 I
LVTTL
31
A6 I
LVTTL
32
A7 I
LVTTL
33
A8 I
LVTTL
34
A9 I
LVTTL
22
A10 I
LVTTL
35
A11 I
LVTTL
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
5
5 Page 
Data Sheet
www.DataSheet4U.com
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
Burst Length
2
Starting Column Address
A2 A1
4
8
FullPage
0
0
0
0
1
1
1
1
n
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TABLE 7
Burst Length and Sequence
Order of Accesses Within a Burst
Type=Sequential
0–1
1–0
0–1–2–3
1–2–3–0
2–3–0–1
3–0–1–2
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
2–3–4–5–6–7–0–1
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
5–6–7–0–1–2–3–4
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
Cn, Cn+1, Cn+2 ....
Type=Interleaved
0–1
1–0
0–1–2–3
1–0–3–2
2–3–0–1
3–2–1–0
0–1–2–3–4–5–6–7
1–0–3–2–5–4–7–6
2–3–0–1–6–7–4–5
3–2–1–0–7–6–5–4
4–5–6–7–0–1–2–3
5–4–7–6–1–0–3–2
6–7–4–5–2–3–0–1
7–6–5–4–3–2–1–0
Not supported
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.32, 2007-10
10122006-I6LJ-WV3H
11
11 Page | ||
| Páginas | Total 21 Páginas | |
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