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PDF MAX1362 Data sheet ( Hoja de datos )
| Número de pieza | MAX1362 | |
| Descripción | 4-Channel 10-Bit System Monitors | |
| Fabricantes | Maxim Integrated Products | |
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19-3268; Rev 3; 4/06
www.DataSheet4U.com
4-Channel, 10-Bit, System Monitors with Programmable
Trip Window and SMBus Alert Response
General Description
The MAX1361/MAX1362 low-power, 10-bit, 4-channel,
analog-to-digital converters (ADCs) feature a digitally
programmable window comparator with an interrupt out-
put for automatic system-monitoring applications. Once
configured, monitor mode automatically asserts an inter-
rupt when any analog input exceeds the programmed
upper or lower thresholds, without interaction to the
host. The MAX1361/MAX1362 respond to the SMBus™
alert, allowing quick identification of the alarming device
on a shared interrupt. A programmable delay between
monitoring intervals lowers power consumption at
reduced monitoring rates.
In addition, the MAX1361/MAX1362 integrate an internal
voltage reference, a clock, and a 1.7MHz, high-speed,
I2C*-compatible, 2-wire, serial interface. The optimized
interface allows a maximum conversion rate of 94.4ksps
in normal mode while reading back the conversion
results. Each of the four analog inputs is configurable for
single-ended or fully differential operation and unipolar
or bipolar operation. Two scan modes utilize on-chip
random access memory (RAM) to allow eight conver-
sions of a selected channel or scanning of a group of
channels to reduce interface overhead.
These devices operate from a single 2.7V to 3.6V
(MAX1361) or 4.5V to 5.5V (MAX1362) supply and
require only 436µA at the maximum sampling rate of
150ksps in monitor mode and 670µA at the maximum
sampling rate of 94.4ksps. AutoShutdown™ powers
down the devices between conversions, reducing sup-
ply current to less than 0.5µA when idle.
The full-scale analog-input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1361 features
a 2.048V internal reference, and the MAX1362 features
a 4.096V internal reference.
The MAX1361/MAX1362 are available in a 10-pin
µMAX® package and are specified over the extended
(-40°C to +85°C) temperature range. For 12-bit applica-
tions, refer to the pin-compatible MAX1363/MAX1364
data sheet.
Applications
System Monitoring/Supervision
Servers/Workstations
High Reliability Power Supplies
Medical Instrumentation
Features
♦ Monitor Mode
Programmable Lower/Upper Trip Threshold
Alarm-Status Register Records Fault Events
SMBus Alert Response
Programmable Sampling Intervals
♦ 10-Bit I2C-Compatible ADC
±1 LSB INL, ±1 LSB DNL
♦ 4-Channel Single-Ended or 2-Channel Fully
Differential Inputs
♦ Software Programmable Bipolar/Unipolar
Conversions
♦ Fast Sampling Rate
94.4ksps While Continuously Reading
Conversions
150ksps in Monitor Mode
♦ High-Speed I2C-Compatible Serial Interface
100kHz/400kHz Standard/Fast Mode
Up to 1.7MHz High-Speed Mode
6 Available I2C Slave Addresses
♦ Single Supply
2.7V to 3.6V (MAX1361)
4.5V to 5.5V (MAX1362)
♦ Internal Reference
2.048V (MAX1361)
4.096V (MAX1362)
♦ External Reference: 1V to VDD
♦ Low Power
436µA in Monitor Mode (150ksps)
670µA at 94.4ksps
6µA at 1ksps
0.5µA in Power-Down Mode
♦ Small Package
10-Pin µMAX
SMBus is a trademark of Intel Corporation.
Purchase of I2C components from Maxim Integrated Products,
Inc. or one of its sublicensed Associated Companies, conveys a
license under the Philips I2C Patent Rights to use these compo-
nents in an I2C system, provided that the system conforms to the
I2C Standard Specification as defined by Philips.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Typical Operating Circuit and Pin Configuration appear at
end of data sheet.
Ordering Information/Selector Guide
PART
TEMP RANGE PIN-PACKAGE I2C SLAVE ADDRESS
SUPPLY
VOLTAGE (V)
PACKAGE
CODE
MAX1361EUB
-40°C to +85°C 10 µMAX
MAX1361LEUB*
-40°C to +85°C 10 µMAX
MAX1361MEUB
-40°C to +85°C 10 µMAX
*Future product—contact factory for availability.
0110100/0110101
2.7 to 3.6
U10C-4
0110010/0110011
2.7 to 3.6
U10C-4
0110110/0110111
2.7 to 3.6
U10C-4
Ordering Information/Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1361), VDD = 4.5V to 5.5V (MAX1362), VREF = 2.048V (MAX1361), VREF = 4.096V (MAX1362), CREF =
0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Hold Time for START (S)
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
SYMBOL
tHD, STA
tLOW
tHIGH
tSU, STA
CONDITIONS
MIN TYP MAX UNITS
0.6 µs
1.3 µs
0.6 µs
0.6 µs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
tHD, DAT
tSU, DAT
tR Measured from 0.3VDD to 0.7VDD
0
100
0
900 ns
ns
300 ns
Fall Time of SDA Transmitting
Setup Time for STOP (P)
Condition
tF
tSU, STO
Measured from 0.3VDD to 0.7VDD
0
0.6
300 ns
µs
Capacitive Load for Each Bus
Line
CB
400 pF
Pulse Width of Spike Suppressed
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12)
Serial Clock Frequency
fSCLH (Note 13)
Hold Time, Repeated START
Condition (Sr)
tHD, STA
160
50 ns
1.7 MHz
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
tLOW
tHIGH
tSU, STA
(Note 13)
320 ns
120 ns
160 ns
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
Rise Time of SCL Signal After
Acknowledge Bit
tHD, DAT
tSU, DAT
tRCL
(Note 14)
Measured from 0.3VDD to 0.7VDD
tRCL1 Measured from 0.3VDD to 0.7VDD
0
10
20
20
150 ns
ns
80 ns
160 ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P)
Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
tFCL
tRDA
tFDA
tSU, STO
CB
Measured from 0.3VDD to 0.7VDD
Measured from 0.3VDD to 0.7VDD
Measured from 0.3VDD to 0.7VDD
20
20
20
160
0
80 ns
160 ns
160 ns
ns
400 pF
10 ns
_______________________________________________________________________________________ 5
5 Page 
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4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
where RSOURCE is the analog-input source impedance,
RIN = 2.5kΩ, and CIN = 22pF. For internal clock mode,
tACQ = 1.5 / fSCL, and for external clock mode tACQ =
2 / fSCL.
Analog-Input Bandwidth
The MAX1361/MAX1362 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals from aliasing into the frequency band of
interest, use anti-aliasing filtering.
Analog-Input Range and Protection
Internal protection diodes clamp the analog inputs to VDD
and GND. These diodes allow the analog inputs to swing
from (GND - 0.3V) to (VDD + 0.3V) without causing dam-
age to the device. For accurate conversions the inputs
must remain within 50mV below GND or above VDD.
Single-Ended/Differential Input
The SE/DIF of the configuration byte configures the
MAX1361/MAX1362 analog-input circuitry for single-
ended or differential input. In single-ended mode (SE/DIF
= 1), the digital conversion results are the difference
between the analog input selected by CS[3:0] and GND.
In differential mode (SE/DIF = 0), the digital conversion
results are the difference between the plus and the minus
analog inputs selected by CS[3:0] (see Tables 5 and 6).
Unipolar/Bipolar
Unipolar mode sets the differential input range from 0
to VREF. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±VREF / 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode. (See
the Transfer Functions section.)
In single-ended mode the MAX1361/MAX1362 always
operate in unipolar mode. The analog inputs are inter-
nally referenced to GND with a full-scale input range
from 0 to VREF (Table 7).
Reference
SEL[1:0] of the setup byte controls the reference and
the AIN3/REF configuration. When AIN3/REF is config-
ured as a reference input or reference output (SEL0 =
1), differential conversions on AIN3/REF appear as if
AIN3/REF is connected to GND. A single-ended conver-
sion in scan mode on AIN3/REF is ignored by an internal
limiter that sets the highest available channel at AIN2
(Table 2).
Internal Reference
The internal reference is 2.048V for the MAX1361 and
4.096V for the MAX1362. SEL0 of the setup byte con-
trols whether AIN3/REF is used for an analog input or a
reference (SEL0 = 0 selects AIN3/REF as AIN3, and
SEL0 = 1 selects AIN3/REF as REF). Decouple
AIN3/REF to GND with a 0.1µF capacitor and a 2kΩ
resistor in series when AIN3/REF is configured as an
internal reference output (SEL[1:0] = 11). See the
Typical Operating Circuit. Once powered up, the refer-
ence remains on until reconfigured. Do not use the ref-
erence to supply current for external circuitry.
External Reference
The external reference ranges from 1V to VDD. For max-
imum conversion accuracy, the reference must deliver
40µA and have an impedance of 500Ω or less. For
noisy or high-output-impedance references, insert a
0.1µF bypass capacitor to GND as close to AIN3/REF
as possible.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s INT/EXT clock bit determines the clock
mode. At power-up, the MAX1361/MAX1362 default to
internal clock mode (INT/EXT clock = 0).
Internal Clock
See the Configuration/Setup Bytes (Write Cycle) section.
In internal clock mode (INT/EXT clock = 0), the MAX1361/
MAX1362 use an internal oscillator for the conversion
clock. The MAX1361/MAX1362 begin tracking the analog
input after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While con-
verting, the MAX1361/MAX1362 hold SCL low (clock
stretching). After completing the conversion, the results
are stored in internal memory. For scan-mode configura-
tions with multiple conversions (see the Scan Modes sec-
tion), all conversions happen in succession with each
additional result stored in memory. Once all conversions
are complete, the MAX1361/MAX1362 release SCL,
allowing it to go high. The master can now clock the
results out in the same order as the scan conversion.
The converted results are read back in a FIFO
sequence. If AIN3/REF is configured as a reference
input or output, AIN3/REF is excluded from multichan-
nel scan. If reading continues past the final result
stored in memory, the pointer wraps around and points
to the first result. Only the current conversion results
are read from memory. The MAX1361/MAX1362 must
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MAX1362.PDF ] | |
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