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PDF ICX428AKL Data sheet ( Hoja de datos )
| Número de pieza | ICX428AKL | |
| Descripción | Diagonal 8mm (Type 1/2) CCD Image Sensor | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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ICX428AKLwww.DataSheet4U.com
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX428AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX248AK, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically through the
adoption of EXview HAD CCDTM technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX248AK and has the same drive conditions.
EXview HAD CCDTM has different spectral
characteristics from the current CCD.
20 pin DIP (Cer-DIP)
Pin 1
2
Features
V
• High sensitivity (+3dB compared with the ICX248AK)
• Low smear (–4dB compared with the ICX248AK)
• High D range
• High S/N
• High resolution and low dark current
3
Pin 11
H 40
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Continuous variable-speed shutter
Optical black position
(Top View)
• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register: 5V drive
12
Device Structure
• Interline CCD image sensor
• Optical size:
Diagonal 8mm (Type 1/2)
• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels
• Chip size:
7.40mm (H) × 5.95mm (V)
• Unit cell size:
8.4µm (H) × 9.8µm (V)
• Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
• Substrate material:
Silicon
TM
∗ EXview HAD CCD is a trademark of Sony Corporation.
EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of
HAD (Hole-Accumulation-Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01507A29
1 page  
ICX428AKL
www.DataSheet4U.com
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max. Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2
–0.05 0 0.05 V
2 VVH = (VVH1 + VVH2)/2
VVH3, VVH4
–0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
–9.6 –9.0 –8.5 V
2 VVL = (VVL3 + VVL4)/2
VφV
8.3 9.0 9.65 Vp-p
2
VφV = VVHn – VVLn (n = 1 to 4)
Vertical transfer clock
voltage
| VVH1 – VVH2 |
VVH3 – VVH –0.25
0.1 V
0.1 V
2
2
VVH4 – VVH –0.25
0.1 V
2
VVHH
0.5 V
2 High-level coupling
VVHL
0.5 V
2 High-level coupling
VVLH
0.5 V
2 Low-level coupling
VVLL
0.5 V
2 Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage∗1
VφH 4.75 5.0
VHL –0.05 0
VRGL
∗1
VφRG
4.5 5.0
VRGLH – VRGLL
5.25 Vp-p
0.05 V
V
5.5 Vp-p
0.8 V
3
3
4
4
4
Low-level coupling
Substrate clock voltage VφSUB
23.0 24.0 25.0 Vp-p
5
∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Item
Reset gate clock
voltage
Symbol
VRGL
VφRG
Min.
Typ.
Max. Unit
Waveform
diagram
–0.2 0 0.2 V
4
8.5 9.0 9.5 Vp-p
4
Remarks
–5–
5 Page 
Image Sensor Characteristics Measurement Method
ICX428AKL
www.DataSheet4U.com
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy Ye Cy Ye
A1
G Mg G Mg
B
Cy Ye Cy Ye
A2
Mg G Mg G
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
– 11 –
11 Page | ||
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