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PDF ICS843004-125 Data sheet ( Hoja de datos )
| Número de pieza | ICS843004-125 | |
| Descripción | FemtoClock Crystal-to-3.3V LVPECL Frequency Synthesizer | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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FemtoClock™ Crystal-to-3.3V
ICS843004-125
LVPECL Frequency Synthesizer
ADVANCE INFORMATION
www.DataSheet4U.com
DATA SHEET
GENERAL DESCRIPTION
The ICS843004-125 is a 4 output LVPECL Syn-
ICS thesizer optimized to generate Ethernet reference
HiPerClockS™ c l o c k f r e q u e n c i e s a n d i s a m e m b e r o f t h e
HiPerClocksTM family of high performance clock
solutions from IDT. The ICS843004-125 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS843004-125 is packaged
in a small 24-pin TSSOP package.
FEATURES
• Four 3.3V LVPECL output pairs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Crystal oscillator designed for 25MHz, 18pF parallel resonant
crystal
• Supports the following output frequency: 125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.58ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
FREQUENCY SELECT FUNCTION TABLE
M Divider Value
25
Inputs
N Divider Value
5
M/N Divider Value
5
Output Frequency (MHz)
(25MHz Ref.)
125
BLOCK DIAGRAM
nPLL_SEL Pulldown
REF_CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
1
0
÷5
M = 25 (fixed)
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
MR Pulldown
PIN ASSIGNMENT
nQ1
Q1
VCCo
Q0
1
2
3
4
24 nQ2
23 Q2
22 VCCO
21 Q3
nQ0
MR
nPLL_SEL
nc
VCCA
nc
VCC
nc
5
6
7
8
9
10
11
12
20 nQ3
19 VEE
18 VCC
17 nXTAL_SEL
16 REF_CLK
15 VEE
14 XTAL_IN
13 XTAL_OUT
ICS843004-125
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
ICS843004AG-125 REVISION A JUNE 3, 2009
1
©2009 Integrated Device Technology, Inc.
1 page  
ICS43004-125 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
www.DataSheet4U.com
TYPICAL PHASE NOISE AT 125MHZ
10Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.58ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
ICS843004AG-125 REVISION A JUNE 3, 2009
5
©2009 Integrated Device Technology, Inc.
5 Page 
ICS43004-125 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
www.DataSheet4U.com
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
V
CC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CCO_MAX
OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CCO_MAX
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V - V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX
OH_MAX
L
CC_MAX
OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V - V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC_MAX
OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843004AG-125 REVISION A JUNE 3, 2009
11
©2009 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS843004-125.PDF ] | |
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